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sensitivity list in systemc


vsreeniv

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Hi

 

I am thinking of moving from verilog to systemc for hardware design.

I have a question about sensitivity list: When I am implementing a logic cloud (not clocked) in verilog, I use the "always @* begin" construct to ensure that all the inputs are in the sensitivity list.

 

Is there a similar construct in systemc, where I don't have to explicitly list all the inputs that can cause the output to change?

 

thanks,

Venkat.

 

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Nope. C++ has no concept of what a sensitivity list is, and no way to figure out what to supply.

 

Remember: SystemC is a library, and C++ is the language. Unless somebody builds a SystemC specific compiler, this won't change.

 

If you are doing RTL design, you are best advised to stick with Verilog, VHDL, or SystemVerilog.

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Hi David,

 

Thanks for the feedback.

 

These advantages of SystemC are leading me to test the waters:

 

1. One can model a system at a higher level of abstraction, and then dive in and do hardware description.

2. Due to its object oriented nature, there might be fewer lines of code (relative to verilog).

3. Free simulation!, Faster simulation using GPUs...

 

But, you are telling me that for RTL design, I should not bother with SystemC?

 

PS: The systems I work on have both analog and digital content and involve DSP.

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