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Parameterised module instantiation


Balakasaiah

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Hi,

 

   I have to instantiate a module multiple times. The Sample code is as below:

 

#define BUS_WIDTH1 32

#define BUS_WIDTH2 16

 

SC_MODULE( mymod )

{

 

   sc_in<sc_bv<BUS_WIDTH1> >       din;

   sc_out<sc_bv<BUS_WIDTH2> >   dout;

 

   sub_mod s1;

 

   SC_CTOR( mymod ): s1(BUS_WIDTH2)

   {

 

       // Port Connections

   }

 

};

 

SC_MODULE( sub_mod )

{

    sc_in<sc_bv<BUS_WIDTH> > in;

     .

     .

     SC_HAS_PROCESS( sub_mod);

     sub_mod(sc_module_name nm,int BUS_WIDTH):sc_module(nm)

     {

 

     }

};

 

I am passing a parameter value BUS_WIDTH2 to sub module and the Sub module parameter is used in the port declaration.....

It is not working...

Can any one suggest a way......?

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[snip]

SC_MODULE( sub_mod )

{

    sc_in<sc_bv<BUS_WIDTH> > in;

     .

     .

     sub_mod(sc_module_name nm,int BUS_WIDTH):sc_module(nm)

     {

 

     }

};

 

The error has got nothing to do with SystemC, the code is not valid C++.. you can't use a constructor parameter ('int BUS_WIDTH') as a parameter to the template instance ('sc_in<sc_bv<BUS_WIDTH> >').

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I am doing port binding as follows:

 

In Top Module:

 

a2a_tc.bid( sig_bid);                  // Error is Showing for this line

wrf.BID( sig_bid );

 

 

a2a_tc, wrf are modules,

bid is an output port of a2a_tc,  i.e  sc_out<sc_uint<4> > bid;        // Here the 4 value is parameterised and is sent to two modules while instantiation

BID is an input port of wrf,          i.e  sc_in<sc_uint<4> > BID;

sig_bid is a signal.                      i.e  sc_signal<sc_uint<4> > sig_bid;

 

instantiations are:

a2a_mod<WIDTH>  a2a_tc;

write_mod<WIDTH> wrf;

 

SC_CTOR( top ):a2a_mod("a2a_mod"),write_mod("write_mod")

{

     // The above shown binging is done in this constructor definition

 

}

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I am still not sure what the error is.

The following works fine: 



#include <systemc>
template < int W >
SC_MODULE(m1)
{
  sc_core::sc_out< sc_dt::sc_uint<W> > out1;
  SC_CTOR(m1) : out1("out1"){}
};

template < int W >
SC_MODULE(m2)
{
  sc_core::sc_in< sc_dt::sc_uint<W> > in1;
  SC_CTOR(m2) : in1("in1"){}
};

template < int W >
SC_MODULE(top)
{
  sc_core::sc_signal< sc_dt::sc_uint<W> > sig;
  
  m1<W> mod1;
  m2<W> mod2;
  
  SC_CTOR(top)
    : mod1("mod1"), mod2("mod2")
  {
    mod1.out1(sig);
    mod2.in1(sig);
  }
};

int sc_main(int, char*[])
{
  top<4> top_mod("top");
  sc_core::sc_start();
  
  std::cout << sc_core::sc_time_stamp() << std::endl;
  return 0;
}

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How about: 





template< int BUS_WIDTH >
SC_MODULE(whatevermodule)
{
  sc_core::sc_in<sc_dt::sc_bv<BUS_WIDTH> > whateverport;
  ...
};

You could do the same for the top level module to avoid the 'define' constants.

 

Greetings

Ralph

In my humble opinion, this solution is sort of a re-direct.

The simplest way, I believe, is to put at top of the source

file the following:

const unsigned int BUS_WIDTH = 32; /* for example */

Then the constant 'BUS_WIDTH' may be used by ANY

module in that source file. Hope that helps.

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  • 3 weeks later...
  • 1 year later...

Hey ralph,

 

I have connect 16 D-Flipflops(submodule) in the form just like 4*4 matrix with Q connecting to the input of next D flipflop in x direction and Q_bar to input of D_flipflop in Y direction....could you suggest a way unlike instantiating a 16 modules like DFF11,DFF2...........DFF16.  

please suggest a way for multiple instantiations (paramaterized instantiation ) and can we do portmapping using for loop in systemC??

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Hey ralph,

 

I have connect 16 D-Flipflops(submodule) in the form just like 4*4 matrix with Q connecting to the input of next D flipflop in x direction and Q_bar to input of D_flipflop in Y direction....could you suggest a way unlike instantiating a 16 modules like DFF11,DFF2...........DFF16.  

please suggest a way for multiple instantiations (paramaterized instantiation ) and can we do portmapping using for loop in systemC??

 

use sc_vector.  Yes, you can bind vector of ports to vector of signals using loop. 

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can u explain in detail....i know it can done in VHDL by for loop for port connections and generate statement for instantiation...but i dont know in systemC

 

 

Here is an example of using sc_vector to create array of modules  and loop to bind ports.

 

 

Suppose you want to delay some signal by N clocks. So you want to connect N D-flipflops in chain (like in shift register). And suppose you want to have N as a paramter.

 

Here is that ""delay_line"" implementation using DFFs :

#include "systemc.h"


SC_MODULE(dff) {

sc_in<bool> clk{"clk"};
sc_in<bool> d{"d"};

sc_out<bool> q{"q"};

SC_CTOR(dff) {
SC_METHOD(update_method);
sensitive << clk.pos();
}

void update_method () {
q = d;
}

};


template <int N>
SC_MODULE(delay_line) {

sc_in<bool> clk{"clk"};
sc_in<bool> d{"d"};

sc_out<bool> q{"q"};

sc_vector< dff > dff_vec{"dff_vec", N};
sc_vector< sc_signal<bool> > dq_vec{"dq_vec", N - 1 };

SC_CTOR(delay_line) {

// bind input of dff chain
dff_vec[0].d(d);

// bind output of dff chain
dff_vec[N-1].q(q);


// bind clock signals for each dff
for (int i = 0; i < N; ++i) {
dff_vec[i].clk(clk);
}

// bind internal dff to dff data signals
for (int i = 0; i < N - 1; ++i) {
dff_vec[i].q(dq_vec[i]);
dff_vec[i+1].d(dq_vec[i]);
}

}

};


template <int N>
SC_MODULE(test) {

sc_clock clk{"clk", 1, SC_NS};
sc_signal<bool> d{"d"};
sc_signal<bool> q{"q"};

delay_line<N> delay_line_inst {"delay_line_inst"};

SC_CTOR(test) {
delay_line_inst.clk(clk);
delay_line_inst.q(q);
delay_line_inst.d(d);

SC_THREAD(test_thread);
sensitive << clk.posedge_event();
}

void test_thread() {
d = 1;
int i = 0;
do {
wait();
cout << "delay line out[" << i++ << " ]: " << q.read() << endl;
} while (!q.read());

}

};

int sc_main(int, char **) {

test<5> delay_line_test{"delay_line_test"};
sc_start();

return 0;
}

You can run this example in Visual Studio 2013 or with GCC 4.8 or later  with -std=c++11  flag

 

 

Please note that it is a low-level style of modeling. You should avoid doing such a low-level stuff, unless you have no other options. 

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