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How to using package rightly in UVM?


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Hi!

 

 

often,in uvm test, host controller write or read registers through  addresses,so, I define some parameter in a package using `define in replace of register address.

   then , import the package into my test lib package,

compile in order , test lib package is compiled lastly,

but when compling code ,report macro address can't find?

How to using package rightly in UVM?

 

Large projects may have many packages with complex interdependencies,How to using it rightly ?

 

 

 

 

thanks.

 

/wszhong

 

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`define won't do the job because that is a compile-time feature.

You should define your constants with sized enum's or const in the package:

Never use `define if you can avoid it, because macros are hard to debug, don't have an underlying data type and have to be recompiled at every turn.

package My_pkg;
  typedef bit [31:0] address_t;
  typedef enum address_t { timer_config_reg = 'h2800; timer_start_reg = 'h2804, timer_current_reg = 'h2808, ... } registers_e;
  const address_t timer_base_addr = 'h2800;
endpackage

Notice that I also abstract the base type because it will likely be used in the verification and design environments. This also makes the code more portable.

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A `define macro is part of the compilation unit and does not belong to any package or other scope. Compiler directives like `define and `ifdef are compiled away as the first step in compilation process before any SystemVerilog syntax is parsed.

 

I would use an actual Verilog parameter inside a package rather than a const variable because parameters can be used in more places than variables; like range declarations. I have a DVCon paper that has a section on explaining the difference between parameters and const variables.

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