ADC modelling in AMS SystemcTLM

[eritronio 0]

The task is to model only the ADC peripheral of the ARM cortex processor (ATSAM3S4A). I have to use the AMS library in order to model the Analog part using timed dataflow. After that, I should connect it to a master module using a TLM interface (blocking or non blocking). This master module should connect to the slave ADC slave peripheral using TLM initiator-target communication.  It should perform the following functions through the programmer view:  ADC_Configuration, ADC_GetStatus, ADC_GetData. I only need to use the channels 3,5 and 7. Then I should connect Sine, Cosine, and Saw tooth waves respectively  using the AMS TDF. The interrupt and timer counter logic is not needed for this task. I should use a header file with the set of registers starting at address 0x40038000 in order to let the SW functions to access the ADC. When these ADC functions execute in the master module, a transaction should be triggered to the ADC slave using the TLM2 protocol. Finally I need to trace the input signals and also the digital conversion of each one in a VCD file. This ADC is 12 bits and it is  required to handle single ended inputs. 

 

So the question would be, how do I start? I'm a total newbie, I would appreciate any help or clue in order to tackle this problem. Image http://postimg.org/image/lywv5n5b9/

[dakupoto 33]

The task is to model only the ADC peripheral of the ARM cortex processor (ATSAM3S4A). I have to use the AMS library in order to model the Analog part using timed dataflow. After that, I should connect it to a master module using a TLM interface (blocking or non blocking). This master module should connect to the slave ADC slave peripheral using TLM initiator-target communication.  It should perform the following functions through the programmer view:  ADC_Configuration, ADC_GetStatus, ADC_GetData. I only need to use the channels 3,5 and 7. Then I should connect Sine, Cosine, and Saw tooth waves respectively  using the AMS TDF. The interrupt and timer counter logic is not needed for this task. I should use a header file with the set of registers starting at address 0x40038000 in order to let the SW functions to access the ADC. When these ADC functions execute in the master module, a transaction should be triggered to the ADC slave using the TLM2 protocol. Finally I need to trace the input signals and also the digital conversion of each one in a VCD file. This ADC is 12 bits and it is  required to handle single ended inputs. 

 

So the question would be, how do I start? I'm a total newbie, I would appreciate any help or clue in order to tackle this problem. Image http://postimg.org/image/lywv5n5b9/

 

As the extent of the project is very big, please use "divide-and-conquer".

First decide on an ADC architecture (flash, dual/single slope or sigma-delat etc.,)

create a module, compile and test with sample input, and ensure that everything

works as per specifications. Then move to the next stage. Please use converter

ports to move data from/to analog/digital modules. Hope that helps.

[Martin Barnasconi 35]

This is a nice assigment; combining the powerful features of plain SystemC, TLM and AMS, for an ARM+ADC subsystem application. This is clearly not a task for a beginner in SystemC - it requires good understanding of all the individual disciplines to model such system. I almost think this is part of an exam or university exercise. But in this forum we will not solve students problems or exams

 

Having said that, here some basic guidance to get started. TLM is primarily used for the bus communication; it does no offer the hooks to model a register interface (RI) or memory map. You should check if your exercise/books/example propose the use of a certain modeling library for these elements. Most EDA vendors offer this type of functionality as non-standard extension for SystemC and TLM. Such register interface defines, as the name suggests, an interface between the bus and the model internals. Register reads/writes via the TLM bus protocol need to trigger certain callbacks in the module, and via these callbacks you can set internal model states or even start signal-level communication to the (TDF) leaf cell(s) in this block.

This should be sufficient info to get started - otherwise ask your teacher