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worma

How do you create sequences in UVM like that in VMM?

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In vmm scenario class, i can write constraints on individual item as well as an items queue, equivalent to which i don't find in VMM

for eg, my 8th item could be predicted looking at the second one or vice versa, how can such a thing be achieved in uvm.

I am looking for a equivalent of the following in uvm :-

Edited by worma

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In UVM it should be slightly easier than that - provided you are familiar with the Sequences part of UVM. I say easier b'cos it is more of "procedural" than declarative as in VMM style - both have their pros-and-cons. Syntax will be quite close as you have conditional constraints in VMM style, that can be mapped easily to uvm_sequence::body() task. Make sure you have enough functional coverage to see the distributions in either case.

If you send/show a full code for a VMM-scenario style, I can perhaps show an equiv. in UVM (than me having to create everything from scratch for you).

Regards

Srini

www.cvcblr.com

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hi worma,

in UVM can have two styles to describe scenarios. the first style (a declarative style) would be similar to what you have shown in your code section. actually it is a set of constraints on an array of transactions. this set of transaction is usually randomized once and then send item-by-item. the second style in uvm is a sequence style which allows you step-wise generation. to illustrate that have a look at the pseudo-code examples below

declarative style:

class uvm1_seq extends uvm_sequence;
// rest of uvm required decls

rand transactions t[5];

constraint legal {
  // your constraints on transaction here
}

virtual task body();
  foreach(transactions[idx])
      // now send the transaction or generate sequence items using the transactions
      // for instance `uvm_do_with(op,{type==transaction[idx].type}
endtask

or with the second style:

class uvmm2_seq extends uvm_sequence;
// rest of required decls
  rand int unsigned scenario_length;
  rand int addr;
  rand int length
virtual task body();
 repeat (scenario_length) 
begin
`uvm_do_with(op,{type inside {my_transaction::MEM_WR_32,my_transaction::MEM_WR_64}; length==uvmm2_seq::length;...})

 // now you can look at op to see what has been sent ( or you can peek into the "transaction store" of the last send transactions
 last_type=op.type;

`uvm_do_with(op,{last_type==M32 -> type==R32; length==uvmm2_seq::length;...})
`
end

Edited by uwes

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I was looking for an equivalent sequence in uvm, one way i did was split it into three sequences and then call them in the body of my_seq. Please let me know if there is an efficient way to do so

Edited by worma

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Here is my version of a sequence from the Practical Guide to UVM, that shows a write followed by a read.

class apb_read_write_word_seq extends uvm_sequence #(apb_transfer);

   `uvm_sequence_utils(apb_read_write_word_seq, apb_master_sequencer);

   rand bit [31:0] start_addr;
   constraint c_addr {start_addr[2:0] == '0; start_addr <= 16'hFFFF;}

   function new(string name="apb_read_write_word_seq");
      super.new(name);
      `uvm_info("INFO", $psprintf("%m"), UVM_HIGH);
   endfunction

   virtual task body();
      `uvm_info("SEQ_NAME", $psprintf("%m"), UVM_HIGH);
      `uvm_do_with(req, {req.addr == start_addr; req.direction == APB_WRITE; });
      `uvm_do_with(req, {req.addr == start_addr; req.direction == APB_READ;  });
   endtask

endclass : apb_read_write_word_seq

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