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samng

SystemC connect to SystemVerilog Interface?

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Hi,

 

I am interested in wrapping a C model with SystemC wrapper to mimic a future RTL design. Is it possible to create a port that can connect directly to a SystemVerilog Interface? For Example:

 

SystemC:

 

struct foo{

   bool valid;

   sc_uint<8> data;

};

 

SC_MODULE (xyz) {

   sc_inout<foo>  port1;

...

};

 

SystemVerilog:

 

interface abc ()

  logic valid;

  logic [7:0] data;

endinterface

 

abc abc_i();

 

xyz (

  .port1(abc_i);

....

);

 

Would this work?

 

Thanks,

Sam

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