a question about the compiling order

[qinhailiang 1]

Hi, all

 

      I fond the function uvm_report_error is called in uvm_object.svh when I read the UVM-1.1d source code, but the file uvm_object.svh is compiled before the file uvm_globals.svh in the file base.svh. Would you please tell me what is wrong with it?

 

      Thanks a lot in advanced!

 

Best Regards

 

QIN

[dave_59 34]

In Verilog, functions/tasks do not need to be defined before they are called. Only data types and variables need to be defined before use.

[qinhailiang 1]

Thanks Dave_59 for your reply！

 

BR

 

QIN