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ljepson74

Free systemverilog/uvm simulator for small amounts of code exists?

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Is there any free systemverilog simulator (w/ UVM support) for small amounts of code?

i.e. perhaps a vendor offers the license for free, to hook newbies and students, restricting them to less than 1000 lines of code or something?

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I don't think there is such a thing.

 

The Altera Modelsim Starter Edition is free, and supports some SystemVerilog (design constructs), but not classes/UVM/constrained random...

That's not completely correct. The Starter/Student editions will support classes. but not calls to class.randomize(), covergroups, or assertions. So you could create some basic UVM structures.

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Hi Dave,

 

As a novice, from the tutorials, all i can remember is, it is necessary to register component using system calls liks `uvm_component_utils or something similar. Now, If i take up a student version of modelsim, it doesn't come with any uvm_library's binary info. So, how can i register any uvm components/objects/sequences and use it?

 

Thanks.

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There is a free browser based IDE for Verilog and SystemVerilog called EDA Playground. It is specifically designed for small prototypes and examples.

Currently, SystemVerilog support is limited to a few features, such as packages: http://www.edaplayground.com/s/4/26

EDA Playground is currently seeking a partner to offer limited public access for UVM simulations.

That said, UVM is fully supported for private deployments. Here is UVM code with sim results: http://www.edaplayground.com/s/4/64

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