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scgenmod utility


chessat2002
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Hi,

I'm currently doing mixed-mode simulations using SystemC testbenches and VHDL/Verilog designs.

For generating SystemC foreign modules, I use the scgenmod utility provided by QuestaSim (V 10.0).

For Verilog designs, I did not face any problems until now.

However, for VHDL designs, scgenmod fails if the top entity contains signed/unsigned data types or generic bitwidths for any data types.

Are there any known work-arounds expect than adapting the entity interface?

Best regards,

Alex'

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