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vcs runtime error with uvm


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Hi, all experts

i met one runtime error as follow. The option "+UVM_PHASE_TRACE" added is used to trance the uvm_phase. It seems like being stuck in some uvm_phase and then generates the vcs runtime internal error? Could anybody give me some clue? Thanks in advance.

Command: ./simv +UVM_VERBOSITY=UVM_LOW +UVM_TESTNAME=test_config +UVM_PHASE_TRACE -l run.log

Chronologic VCS simulator copyright 1991-2012

Contains Synopsys proprietary information.

Compiler version G-2012.09; Runtime version G-2012.09; Dec 26 12:19 2012

----------------------------------------------------------------

UVM-1.1c

© 2007-2012 Mentor Graphics Corporation

© 2007-2012 Cadence Design Systems, Inc.

© 2006-2012 Synopsys, Inc.

© 2011-2012 Cypress Semiconductor Corp.

----------------------------------------------------------------

*********** IMPORTANT RELEASE NOTES ************

You are using a version of the UVM library that has been compiled

with `UVM_NO_DEPRECATED undefined.

See http://www.eda.org/svdb/view.php?id=3313 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test_config...

UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common' (id=55) Starting phase

UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common' (id=55) Completed phase

UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.build' (id=73) Scheduled from phase common

UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.build' (id=73) Starting phase

UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common.build' (id=73) Completed phase

UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.connect' (id=85) Scheduled from phase common.build

UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.connect' (id=85) Starting phase

UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common.connect' (id=85) Completed phase

UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.end_of_elaboration' (id=97) Scheduled from phase common.connect

UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.end_of_elaboration' (id=97) Starting phase

UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common.end_of_elaboration' (id=97) Completed phase

UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.start_of_simulation' (id=109) Scheduled from phase common.end_of_elaboration

UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.start_of_simulation' (id=109) Starting phase

UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common.start_of_simulation' (id=109) Completed phase

UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.run' (id=121) Scheduled from phase common.start_of_simulation

UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm' (id=170) Scheduled from phase common.start_of_simulation

UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.run' (id=121) Starting phase

UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'uvm' (id=170) Starting phase

Command line: ./simv./simv +UVM_VERBOSITY=UVM_LOW +UVM_TESTNAME=test_config +UVM_PHASE_TRACE -l run.log

+UVM_VERBOSITY=UVM_LOW +UVM_TESTNAME=test_config +UVM_PHASE_TRACE -l run.log

Command line: ./simv +UVM_VERBOSITY=UVM_LOW +UVM_TESTNAME=test_config +UVM_PHASE_TRACE -l run.log

--- Stack trace follows:

No context available

VCS runtime internal error (core dumped) .

Please contact vcs_support@synopsys.com or call 1-800-VERILO

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Hi,

Have you used "-full64 -debug_all" options in your compilation command?

If not, try with these options. If still it doesn't work add another option "-picarchive"

Regards

Peer Mohammed

I have added the option "-debug_all" and "-picarchive", it didn't work. When i used the option "-full64" it reported as follow,

ERROR - /EDA_Tools/synopsys/vcs1209/amd64/bin is not valid directory, is VCS_HOME set correctly?

make: *** [comp] Error 255

$VCS_HOME=/EDA_Tools/synopsys/vcs1209, i think it is right. And I find that there isn't any */amd64/ sub directory in directory /EDA_Tools/synopsys/

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Hi, Peer Mohammed

I have added the options "-full64 -debug_all -picarchive" after restalling vcs(install *common.tar *amd64.tar and *linux.tar), it still didn't work. but i cann't get the information vcs runtime internal error now, the procedure is just stuck at the line:

UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'uvm' (id=170) Starting phase

Does it mean that i should trace the uvm_phase mannualy?

Best Regards

mrforver

Hi,

Have you used "-full64 -debug_all" options in your compilation command?

If not, try with these options. If still it doesn't work add another option "-picarchive"

Regards

Peer Mohammed

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Hi,

open gui and view phase debugger pane. See which objections are active.

Also open sequence debug pane and seee if any sequences are active.

If you press break in gui it will show all active threads in thread window. There will be probably be too many threads to debug but you might see something obvious if you are lucky.

The fact you are running with f4bit switch means simulation will be much slower and handle more memory. Perhaps the previous issue was a memory issue that caused the crash.

I would never use 64bit unless I was comppiling big design.

-adiel

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Hi,

open gui and view phase debugger pane. See which objections are active.

Also open sequence debug pane and seee if any sequences are active.

If you press break in gui it will show all active threads in thread window. There will be probably be too many threads to debug but you might see something obvious if you are lucky.

-adiel

Hi, adiel

Thanks for your seguestion.

I have tried that way, but it appeared that there wasn't any active phase in the phase debugger pane. But the reports above [PH/TRC/SCHEDULED] Phase 'common.run' (id=121) Scheduled from phase common.start_of_simulation implies that the procedure should have reached the start_of_simulation phase. I suppose that there should be active end_of_elaboration phase or active start_of_simulation phase. I don't know why there was not any active phase.

By the way, how can I see the active sequences?

Regards

mrforever

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