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Hi All, I have a case using "diamond inheritance" sc_module as below figure base / \ A B \ / top base=> struct to share A and B A => a systemc module (virtual public sc_module) B => a systemc module (virtual public sc_module) top=> a systemc module (virtual public A, virtual public B ) it work fine. But when I using SC_THREAD. the compiler shows error, "pointer to member conversion via virtual base". is it possible to fix the error? Thanks
I am trying to extend uvm_cmdline_processor as follows, but my extended version, ivm_cmdline_processor is not working. It seems like the *ref values* might not be getting passed correctly. There is no error message. The get_arg_values that is called with iclp is seen I know, because I receive a simulator warning about not using a void'() with the function. (This warning occurs for both the uclp and iclp usages, as expected.) I am not sure about my duplication of the get_inst function to create and return a singleton, but have tried versions of this code w/ and w/o it. `include "ivm_cmdline_processor.svh" module top; import uvm_pkg::*; ivm_cmdline_processor iclp; uvm_cmdline_processor uclp; string values[$]; initial begin $display(">>>> START TEST."); iclp=ivm_cmdline_processor::get_inst(); uclp=uvm_cmdline_processor::get_inst(); iclp.get_arg_values("+",values); foreach (values[iii]) begin $display("iclp>>>%0d: %0s", iii, values[iii]); end uclp.get_arg_values("+",values); foreach (values[iii]) begin $display("uclp>>>%0d: %0s", iii, values[iii]); end $display(">>>> END TEST."); end endmodule : top import uvm_pkg::*; class ivm_cmdline_processor extends uvm_cmdline_processor; static local ivm_cmdline_processor m_inst; static function ivm_cmdline_processor get_inst(); if(m_inst == null) m_inst = new("ivm_cmdline_proc"); return m_inst; endfunction function new(string name = ""); super.new(.name(name)); endfunction : new endclass : ivm_cmdline_processor Reason for attempt: I would like to add features to the uvm_cmdline_processor. To start, I'd like to enhance +arg checking by checking that the +args supplied are from a list of valid +args. Typos are too common from my fingers and without this functionality, typos go unnoticed. (Once I even was in a different sim environment than I thought and was happily running a test with plusargs for a completely different testbench, wondering why things weren't working as I expected.) I realize that I might create an object or 'shell', around uvm_cmdline_processor and do my checking in this 'shell'. I have a version of this now, but I'd like to make it generic so that it may be used across 'all' testbenches. Rather than polishing my shell, I am first trying to extend uvm_cmdline_processor and running into these problems. Any ideas about this? (I just discovered this next post from about 30min ago. Thanks, Srini. I think my problem is the same, but am not sure as I am not trying to 'mix' which handle (parent or child) points to my extended version of uvm_cmdline_processor. Yes, I am confused about this. re: http://forums.accellera.org/topic/1937-uvm-cmdline-processor-why-its-methods-are-non-virtual/ )