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Hi, I wonder if we can create sequence library of virtual sequences? I know uvm supports uvm_sequence_library class where we can create library of uvm_sequence. can we do same for virtual sequences? If yes can anyone give me example? Thanks, Akshay

Hello Everyone, I am trying to control a sub virtual sequencer's non-virtual sub sequencers using a top level virtual sequencer. It looks like this diagram. <start of diagram> .------------------------------------------------------. | my_test | .--------------------------------------------------. | | | sequences | | | '--------------------------------------------------' | | .--------------------------------------------------. | | | my_env | | | '--------------------------------------------------' | '/----------------------------------------------------\' / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ .----------------------------------------------------------------------------------------------------. | my_env | | .------------------------. | | | my_virtual_sequencer | | | '------------------------' | | .-----------------------------------. .----------------------------. .---------------------------. | | | sub_virtual_agent | | sub_agent_a | | sub_agent_b | | | | .-------------------------------. | | .------------------------. | | .-----------------------. | | | | | sub_virtual_sequencer | | | | sub_sequencer_a | | | | sub_sequencer_b | | | | | '-------------------------------' | | '------------------------' | | '-----------------------' | | | | .-------------------------. | | .------------------------. | | .-----------------------. | | | | | sub_agent_3 | | | | driver_a | | | | driver_b | | | | | .-------------------------. | | | '------------------------' | | '-----------------------' | | | | | sub_agent_2 | | | | .------------------------. | | .-----------------------. | | | | .---------------------------. | | | | | monitor_a | | | | monitor_b | | | | | | sub_agent_1 | | | | | '------------------------' | | '-----------------------' | | | | | .-----------------------. | | | | '----------------------------' '---------------------------' | | | | | sub_sequencer_1 | | | | | | | | | '-----------------------' | | | | | | | | .-----------------------. | | | | | | | | | driver_1 | | | | | | | | | '-----------------------' | | | | | | | | .-----------------------. | | | | | | | | | monitor_1 | | |-' | | | | | '-----------------------' |-' | | | | '---------------------------' | | | '-----------------------------------' | '----------------------------------------------------------------------------------------------------' <end of diagram> I am trying to apply section 4.8 Virtual Sequences of uvm users guide. But I think I am missing on something. I have a top level virtual sequence that has the top level virtual sequencer as its p_sequencer. I have this in the macro: `uvm_declare_p_sequencer(my_virtual_sequencer) And then I have this in the task body() to access the sub sequencer of the sub virtual sequencer: `uvm_do_on(sub_sequence_1, p_sequencer.i_sub_virtual_sequencer.i_sub_sequencer_1); sub_sequence_1 is a physical sequence. Is this correct under the UVM standard? If not, how do I properly control i_sub_sequencer_1? This is how I access it in the test build_phase: uvm_config_db #(uvm_object_wrapper)::set(this, "i_my_env,i_my_virtual_sequencer.main_phase","default_sequence",my_virtual_sequence::type_id::get()); Any help/inputs to this is much appreciated. Thanks, Martin

Hi All, I have a question regarding the proper placement of the following code for raising an objection in a multi-layered testbench (i.e. virtual sequencer -> virtual sub sequencer -> sub sequencer): <start snip> virtual task pre_start(); if(starting_phase != null) starting_phase.raise_objection(get_sequencer()); endtask <end snip> I have tested the physical sequences and they work when no virtual sequences are involved. With that isolated, I introduced the 2 virtual sequences and since the new default_sequence is the top virtual sequence, I placed a raise_objection there. Here is a summary of my trial runs: 1) Pure physical sequence as default_sequence - raise_objection at physical sequence (works); 2) Top virtual sequnce as default_sequence - raise_objection added to virtual sequence's pre_start (does not work); What happens to 2) is the top virtual sequence does not end but the sub sequences do not run either. Please shed some light on why this is happening and possible ways to fix this. Thanks, Martin

Hi all, I have ran into the problem about virual sequence's starting Here are the codes: class my_env extends uvm_env; ... master_vsequence v_seq[]; ... function void build_phase(uvm_phase phase); ... v_seq = new[host_num]; for (int i = 0; i < host_num; i++) begin v_seq[i] = master_vsequence::type_id::create($sformatf("v_seq[%0d]", i), this); ... endfunction: build_phase ... task run_phase(uvm_phase phase); //fork // update_vif_enables() //join $display("Starting virtual sequence!!!") fork for (int i = 0; i < host_num; i++) begin v_seq[i].starting_phase = phase; slv_seq[i].starting_phase = phase; v_seq[i].start(subenv[i].v_sqr); slv_seq[i].start(subenv[i].slv_agt.slv_sqr); end join endtask : run_phase ... endclass: my_env class my_subenv extends uvm_env function void build_phase(uvm_phase phase) inst_name = $sformatf("v_sqr%0d", id); v_sqr = vsequencer::type_id::create(inst_name, this); //uvm_config_db#(uvm_object_wrapper)::set(this, {inst_name, ".run_phase"}, "default_sequence", master_vsequence::type_id::get()); ... endfunction: build_phase ... function void connect_phase(uvm_phase phase) string inst_name; super.connect_phase(phase); inst_name = $sformatf("v_sqr%0d", id); uvm_config_db#(config_sequencer)::set(this, inst_name, "cfg_sqr", this.cfg_agt.cfg_sqr); uvm_config_db#(string_sequencer)::set(this, inst_name, "str_sqr", this.str_agt.str_sqr); endfunction : connect_phase ... endclass : my_subenv class master_vsequence extends uvm_sequence; ... function new(string name = "master_vsequence"); ... cfg_seq = config_sequence::type_id::create("cfg_seq",,get_full_name()); str_seq = string_sequence::type_id::create("str_seq",,get_full_name()); ... endfunction virtual task body(); `uvm_do_on(cfg_seq, p_sequencer.cfg_sqr) `uvm_do_on(str_seq, p_sequencer.str_sqr) //cfg_seq.start(p_sequencer.cfg_sqr) //str_seq.start(p_sequencer.str_sqr) endtask: body `uvm_declare_p_sequencer(vsequencer) endclass : master_vsequence class vsequencer extends uvm_sequencer; // subsequenc config_sequencer cfg_sqr; string_sequencer str_sqr; function void build_phase(uvm_phase phase) string inst_name; super.build_phase(phase); // instantiates sequencers and config; inst_name = $sformatf("vcfg_sqr%0d", ID); cfg_sqr = config_sequencer::type_id::create(inst_name, this); void'(uvm_config_db#(config_sequencer)::get(this, "", inst_name, cfg_sqr)); inst_name = $sformatf("vstr_sqr%0d", ID); str_sqr =string_sequencer::type_id::create(inst_name, this); void'(uvm_config_db#(string_sequencer)::get(this, "", inst_name, str_sqr)); endfunction : build_phase endclass: vsequence When I run these codes, It prints"Starting virtual sequence!!!" on screen, then stucks. Seems like the virtual sequence doesn't start. Is there any problem about starting virtual sequence as above? By the way, the config_sequence will start successly if I don't use virtual sequence and string_seuquece.