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Showing results for tags 'verilog'.
I wish to monitor two signals and wish to determine which of the two changes first and then do some work. module tb( input sel1, input sel2 ); //Determining which of the two changes first // if sel1 changed first //do some work //else //do some other work endmodule There are two signals sel1 and sel2 and I wish to monitor which of the following changed first and then do some work. Can someone help me in doing the same. Thank you.
I have to write a code that can be synthesised in verilog language and it displays a few values. I need to display the read and write data being read/written to some registers using the AHB protocol. I successfully displayed the write data but I am stuck in displaying the read data. Since the read appears after some time, I couldn't find a way to capture and display the read data. Initially I thought of this : @(negedge clk) wait(rdata) $fdisplay(rdata) But there could be multiple non-zero Read transactions. Now i am stuck here : @(negedge clk) //wait for rdata t
Hi, I am using the IPXACT 2009 standard to describe a verilog module. The module has a bunch of parameters and ports whose width depends on these parameters. I had a couple of questions regarding this: 1) Do the parameters go under "<spirit:model>..<spirit:modelParameters>" or under ""<spirit:model><spirit:views><spirit:view><spirit:parameters>" ? 2) From what I understand, there seems to be way to describe variable width ports in the 2014 standard but not in the 2009 standard? Thanks.