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Showing results for tags 'variable part select'.
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Hi all, I have one problem about variable part select of Verilog. If you know the width, but the upper or lower range is a variable, you can use variable part select. eg : addr[idx_bits-:8] = {8{1'b1}}; t's okay. But if you know the upper or lower range, the width is a variable, how can you do? I adapt the similar way of variable part select. eg: addr[8-:idx_bits] = {idx_bits{1'b1}}; VCS reports such an error: Error-[NCE] Non-constant expression The following expression should be a constant. Expression: idx_bits Source info: addr[8-:idx_bits] = {idx_bits{1'b1}}; Could anybody help to have a look? Thanks in advance.