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Hi all, I'm new with UVM and I came across a problem. I am working on an AXI RD VIP using UVM and I have the following issue. In the data_phase (the data channel driving) from the MASTER driver, I need to drive the RREADY signal. There are 3 handshake types described in the protocol specifications: valid before ready, ready before valid and ready and valid at the same time. In case of valid before ready, I want to wait a certain number of clock cycles ( delay ) from the time that RVALID asserted and then to assert the RREADY signal. From my understanding, all the delay information s