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Showing results for tags 'uvm reg model'.
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Hi , What is the exact difference between the predefined uvm bit bash and uvm frontdoor sequence. When both the sequence are doing the register access through front door, why is the need of a separate uvm frontdoor sequence ?
Register read via register model.
sega posted a topic in UVM SystemVerilog DiscussionsI am reading a register with using uvm_reg method read_reg. so while doing this read transaction is happening on to the actual bus through agent ,but the I am not getting read value in read_reg task in to a register sequence. so I want to know what could be the issue for not getting read value on to the read_reg task. Regards sega