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Hello, Assuming cycle accuracy is not needed, Is it possible to model external interfaces such as PIPE using standard TLM interfaces? If so, how do I take care of addressing in TLM interface to model an external interface that is not memory-mapped. Any suggestion is appreciated. Thank you.

Hello All I am trying to list out all the ports, sockets in a given SystemC platform. For that I am traversing the hierarchy using sc_get_top_level_object/get_child_object and able to list out all the ports and sockets. But for TLM 2 sockets I get two entries there for example - top_inst.init_inst.initiator_socket - top_inst.init_inst.initiator_socket_export_0 and - top_inst.memory_inst.target_socket - top_inst.memory_inst.target_socket_port_0 It is obvious because each TLM2 socket internally have one port and one sc_export. Is there a way that I get only those sockets which are visible in SystemC model header file for example I want to have only the following - top_inst.init_inst.initiator_socket - top_inst.memory_inst.target_socket Thanks Khushi

Hello All I have a confusion regarding the BUSWIDTH template with TLM2 sockets. In TLM sockets e.g. tlm_initiator_socket/simple_target_socket, why we have BUSWIDTH template and what is the need for this. If I want to transfer 256 bit data from an initiator (with tlm_initiator_socket port on it) to a target (with tlm_target_socket port on it), I can do it in one go by setting the data length and data pointer payload fields appropriately irrespective of the BUSWIDTH template. Whether I use BUSWIDTH 1 or 8 or 16 or 32 and so on, I can still call the b_transport and transfer the data in one go. So what is the significance of this BUSWIDTH template parameter. Where it is actually makes a difference. Thanks Khushi

Dear Guys, I have got a compile error as bellow: .../sc_interface.h:67: error: 'sc_core::sc_interface::sc_interface(const sc_core::sc_inteface&)' is private ../producer.h:33: error: within this context ...... My sc code here: producer.h class producer : public uvm_component , public tlm::tlm_bw_transport_if<tlm::tlm_base_protocol_types> { public: tlm::tlm_initiator_socket<32,tlm::tlm_base_protocol_types> b_isocket; tlm::tlm_initiator_socket<32,tlm::tlm_base_protocol_types> nb_isocket; producer(sc_module_name nm) : uvm_component(nm) , b_isocket("b_isocket") , nb_isocket("nb_isocket") { b_isocket(*this); nb_isocket(*this); } UVM_COMPONENT_UTILS(producer) void build() { cout << "SC producer::build" << endl; } ...... } sctop.cpp: #include "uvm_ml.h" #include "ml_tlm2.h" using namespace uvm; using namespace uvm_ml; #include "uvm_ml_transaction.h" #include "sc_global_define.h" #include "sc_env.h" #include "producer.h" class sctop : public uvm_component { public: sc_env * scenv; producer prod; sctop(sc_module_name nm) : uvm_component(nm), prod(prod) { cout << "SC sctop::sctop name= " << this->name() << " type= " << this->get_type_name() << endl; } void build() { cout << "SC sctop::build " << this->name() << endl; scenv = new sc_env("scenv"); } void before_end_of_elaboration() { cout << "SC sctop::before_end_of_elaboration " << this->name() << endl; std::string full_initiator_b_socket_name = ML_TLM2_REGISTER_INITIATOR(prod, PAYLOAD_TYPE, b_isocket , 32); std::string full_initiator_nb_socket_name = ML_TLM2_REGISTER_INITIATOR(prod, PAYLOAD_TYPE, nb_isocket , 32); uvm_ml::uvm_ml_connect(full_initiator_b_socket_name, "test.svenv.sv_ref_model.b_target_socket"); uvm_ml::uvm_ml_connect(full_initiator_nb_socket_name, "test.svenv.sv_ref_model.nb_target_socket"); } void connect() { cout << "SC sctop::connect " << this->name() << endl; if (scenv->ref_model != NULL) { uvm_ml_register(&scenv->ref_model->sc_to_sv_port1); uvm_ml_register(&scenv->ref_model->sc_to_sv_port2); } uvm_ml_register(&scenv->data->sv_to_sc_data_export); uvm_ml_register(&scenv->config->sv_to_sc_config_export); } void start_of_simulation() { cout << "SC sctop::start_of_simulation " << this->name() << endl; } void end_of_elaboration() { cout << "SC sctop::end_of_elaboration " << this->name() << endl; } UVM_COMPONENT_UTILS(sctop) }; UVM_COMPONENT_REGISTER(producer) UVM_COMPONENT_REGISTER(sctop) int sc_main(int argc, char** argv) { return 0; } UVM_ML_MODULE_EXPORT(sctop) Can you help me with this?

Hello, I'm trying to compile a design with a TLM2 socket (simple_initiator_socket) in ModelSim (sccom). So far, the compiler returns an error saying that there is no function called b_transport. Yet I have this same design working in the PoC SC simulator, so I'm guessing that ModelSim is doing things differently than the PoC. However ModelSim does point out an alternative, which was to use blocking_transport_if's version. I believe this was the one used all along in the PoC, and it should be the same in ModelSim. Any ideas? Here are the designs: Initiator /** * RTL-to-TLM2 Adaptor */ ... /** Includes **/ ... #include <tlm.h> #include <tlm_utils/simple_initiator_socket.h> ... struct rtl_to_tlm2_adaptor: public sc_channel { /** TLM-2 simple initiator socket **/ tlm_utils::simple_initiator_socket<rtl_to_tlm2_adaptor> rtt2a_socket; ... /** Adaptor constructor **/ SC_HAS_PROCESS( rtl_to_tlm2_adaptor ); rtl_to_tlm2_adaptor(sc_module_name _name) : sc_module(_name), addr(0), data(0), cmd(tlm::TLM_IGNORE_COMMAND) { // Construct and name socket SC_THREAD(write_thread); // Register adaptor channel thread SC_THREAD(read_thread); // Register read/write method trans = new tlm::tlm_generic_payload; // Create new payload instance } private: ... // Variables defined here /** Methods **/ // Sets up TLM2 payload void payload_setup(tlm::tlm_generic_payload* trans, tlm::tlm_command cmd, signed short& data, uint64 addr) { // Initialize 8 out of the 10 TLM-2 attributes, byte_enable_length and extensions being unused trans->set_command(cmd); trans->set_address(addr); trans->set_data_ptr(reinterpret_cast<unsigned char*>(&data)); trans->set_data_length(MEM_DATA_WORD_LEN); trans->set_streaming_width(MEM_DATA_WORD_LEN); trans->set_byte_enable_ptr(0); trans->set_dmi_allowed(false); trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); } // Local b_transport used to execute the standard TLM2 procedures void local_b_transport() { payload_setup(trans, cmd, data, addr); // Payload setup rtt2a_socket->b_transport(*trans, sc_time(SC_ZERO_TIME)); // Blocking transport call // Initiator obliged to check response status and delay if (trans->is_response_error()) SC_REPORT_ERROR("TLM-2", "Response error from b_transport"); } // Memory write procedure void mem_write() { cmd = tlm::TLM_WRITE_COMMAND; // Set command ... local_b_transport(); // Call local b_transport ... } // Memory read procedure void mem_read() { cmd = tlm::TLM_READ_COMMAND; // Set command ... local_b_transport(); // Call local b_transport ... } }; #endif Target /** * Generic memory instance, mostly inspired by Doulos' example */ ... /** Includes **/ #include <tlm.h> #include <tlm_utils/simple_target_socket.h> ... struct gen_mem: sc_module { /** TLM-2 simple target socket **/ tlm_utils::simple_target_socket<gen_mem> mem_socket; /** Generic memory constructor **/ SC_CTOR(gen_mem) : mem_socket("mem_socket") { // Register callback for incoming b_transport interface method call mem_socket.register_b_transport(this, &gen_mem::b_transport); dont_initialize(); // Mark to not initialize thread // Initialize memory with random data mem_reset(); } // TLM-2 blocking transport method virtual void b_transport(tlm::tlm_generic_payload& trans, sc_time& delay) { tlm::tlm_command cmd = trans.get_command(); // Get command sc_dt::uint64 adr = trans.get_address(); // Get address unsigned char* ptr = trans.get_data_ptr(); // Get data pointer unsigned int len = trans.get_data_length(); // Get data length unsigned char* byt = trans.get_byte_enable_ptr(); // Get byte enable pointer unsigned int wid = trans.get_streaming_width(); // Get streaming width // Obliged to check address range and check for unsupported features if (adr >= sc_dt::uint64(MEM_SIZE) || byt != 0 || len > 16 || wid < len) SC_REPORT_ERROR("TLM-2", "Target does not support given generic payload transaction"); // Obliged to implement read and write commands if (cmd == tlm::TLM_READ_COMMAND) { // Read command memcpy(ptr, &mem[adr], len); // Use memcopy function to copy memory address pointer // cout << sc_time_stamp() << " MEMORY: Reading value " << *(mem+adr) << " @" << adr << endl; } else if (cmd == tlm::TLM_WRITE_COMMAND) { // Write command memcpy(&mem[adr], ptr, len); // Use memcopy function to copy to memory // cout << sc_time_stamp() << " MEMORY: Writing value " << *ptr << " @" << adr << endl; } else if (cmd == tlm::TLM_IGNORE_COMMAND) { // Reset command mem_reset(); // Reset memory // cout << sc_time_stamp() << " MEMORY: Reset requested" << endl; } else SC_REPORT_ERROR("TLM-2", "Command not supported"); // Obliged to set response status to indicate successful completion trans.set_response_status(tlm::TLM_OK_RESPONSE); // Realize wait delay to advance simulation time wait(delay); } private: unsigned short mem[MEM_SIZE]; // Memory array instance void mem_reset() { for (int i = 0; i < MEM_SIZE; i++) mem[i] = 0x21; // 33 in decimals } }; #endif Error printout # Model Technology ModelSim PE sccom 10.4a compiler 2015.03 Mar 25 2015 # # In file included from source/testbench/../module/c/memory.h:11, # from source/testbench/cpu_testbench.h:11, # from source/testbench/cpu_testbench.cpp:5: # source/testbench/../module/c/rtl_to_tlm2_adaptor.h: In member function 'void rtl_to_tlm2_adaptor::local_b_transport()': # source/testbench/../module/c/rtl_to_tlm2_adaptor.h:148: error: no matching function for call to 'tlm::tlm_fw_transport_if<tlm::tlm_base_protocol_types>::b_transport(tlm::tlm_generic_payload&, sc_core::sc_time)' # C:/modeltech_pe_10.4a\include\systemc/tlm_core/tlm_2/tlm_2_interfaces/tlm_fw_bw_ifs.h:54: note: candidates are: void tlm::tlm_blocking_transport_if<TRANS>::b_transport(TRANS&, sc_core::sc_time&) [with TRANS = tlm::tlm_generic_payload]

Hi, I am getting errors like below: Trace ERROR: No traces can be added once simulation has started. To add traces, create a new vcd trace file. Code of memory.cpp corresponding to error: Memory::Memory(sc_core::sc_module_name name, unsigned int size) : sc_module(name), m_size(size) { tf = sc_core::sc_create_vcd_trace_file("trace_data1"); // tracing, trace file creation tf->set_time_unit(10, sc_core::SC_US); storage = new ensitlm::data_t[size/sizeof(ensitlm::data_t)]; } // Destructor Memory::~Memory() { // close trace file sc_close_vcd_trace_file(tf); delete [] storage; } // Read transactions tlm::tlm_response_status Memory::read(ensitlm::addr_t a, ensitlm::data_t& d) { // Check if the address is within memory bounds if (a >= m_size) { sleep(5); return tlm::TLM_ADDRESS_ERROR_RESPONSE; } else { d = storage[a/sizeof(ensitlm::data_t)]; sc_trace(tf, d ,"d"); return tlm::TLM_OK_RESPONSE; } } // Write transactions tlm::tlm_response_status Memory::write(ensitlm::addr_t a, ensitlm::data_t d) { // Check if the address is within memory bounds if (a >= m_size) { sleep(5); return tlm::TLM_ADDRESS_ERROR_RESPONSE; } else { storage[a/sizeof(ensitlm::data_t)] = d; return tlm::TLM_OK_RESPONSE; } } code of memory.h : SC_MODULE(Memory) { ensitlm::target_socket<Memory> target; sc_core::sc_trace_file *tf; Memory(sc_core::sc_module_name name, unsigned int size); ~Memory(); tlm::tlm_response_status read(ensitlm::addr_t a, ensitlm::data_t& d); tlm::tlm_response_status write(ensitlm::addr_t a, ensitlm::data_t d); private: unsigned int m_size; public: /* The loader must have access to the storage */ ensitlm::data_t* storage; }; #endif Please tell me the reasons behind these errors Regards Hakimelectronics