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Found 5 results

  1. Hello All I am trying to list out all the ports, sockets in a given SystemC platform. For that I am traversing the hierarchy using sc_get_top_level_object/get_child_object and able to list out all the ports and sockets. But for TLM 2 sockets I get two entries there for example - top_inst.init_inst.initiator_socket - top_inst.init_inst.initiator_socket_export_0 and - top_inst.memory_inst.target_socket - top_inst.memory_inst.target_socket_port_0 It is obvious because each TLM2 socket internally have one port and one sc_export.
  2. Hello All I have a confusion regarding the BUSWIDTH template with TLM2 sockets. In TLM sockets e.g. tlm_initiator_socket/simple_target_socket, why we have BUSWIDTH template and what is the need for this. If I want to transfer 256 bit data from an initiator (with tlm_initiator_socket port on it) to a target (with tlm_target_socket port on it), I can do it in one go by setting the data length and data pointer payload fields appropriately irrespective of the BUSWIDTH template. Whether I use BUSWIDTH 1 or 8 or 16 or 32 and so on, I can still call the b_transport and transfer th
  3. Dear Guys, I have got a compile error as bellow: .../sc_interface.h:67: error: 'sc_core::sc_interface::sc_interface(const sc_core::sc_inteface&)' is private ../producer.h:33: error: within this context ...... My sc code here: producer.h class producer : public uvm_component , public tlm::tlm_bw_transport_if<tlm::tlm_base_protocol_types> { public: tlm::tlm_initiator_socket<32,tlm::tlm_base_protocol_types> b_isocket; tlm::tlm_initiator_socket<32,tlm::tlm_base_protocol_types> nb_isocket; producer(sc_modul
  4. Hello, I'm trying to compile a design with a TLM2 socket (simple_initiator_socket) in ModelSim (sccom). So far, the compiler returns an error saying that there is no function called b_transport. Yet I have this same design working in the PoC SC simulator, so I'm guessing that ModelSim is doing things differently than the PoC. However ModelSim does point out an alternative, which was to use blocking_transport_if's version. I believe this was the one used all along in the PoC, and it should be the same in ModelSim. Any ideas? Here are the designs: Initiator /** * RTL-t
  5. Hi, I am getting errors like below: Trace ERROR: No traces can be added once simulation has started. To add traces, create a new vcd trace file. Code of memory.cpp corresponding to error: Memory::Memory(sc_core::sc_module_name name, unsigned int size) : sc_module(name), m_size(size) { tf = sc_core::sc_create_vcd_trace_file("trace_data1"); // tracing, trace file creation tf->set_time_unit(10, sc_core::SC_US); storage = new ensitlm::data_t[size/sizeof(ensitlm::data_t)]; } // Destructor Memory::~Memory() { // close trace file sc_close_vcd_trace_file(tf); delete []
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