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Showing results for tags 'timer'.
I am new to SystemC, and this is my first program. I have timer module already built. sc_main should contain the following points: Instantiation of timer module Trace ports/variable: clock start timeout count start signal to create a trace which contains a waveform of exactly 30 cycles (300ns, that is.) This 30-cycle waveform should include following scenarios: reset the timer for 3 cycles before it is released for counting, during counting reset the timer before count reaches 0, and during counting reset the timer after co
Hi all, i'm implementing a timer/counter(8-bit) that should not increment on every clock and i'm not supposed to provide any input clock port . But i need clock period in my design so my question is " How would i provide clock period(through constructor)?" here is the link to my working code on EDAplayground : http://www.edaplayground.com/x/4_dY if there is any problem in my code please feel free to tell me. regards, jatin
Hi All: Get to implement a timer module in SytemC-TLM. And it is at LT level. The Time used for interrupt generation is from sc_time_stamp. My current implementation is using TLM payload event queue, which means the timer caculates the expected wait time for the request and do "notify(x ns)" for the payload event queue. Which the drawback is: 1.When I add the cancel function for a ongoing time request, I can't delete the "time request" from the event queue. I do a workaround like saving some tags when the timeout happened to achieve the "cancel" 2.When I add a stop function