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Showing results for tags 'time step'.
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time slot vs. time step (1800.1-2017.pdf)
ljepson74 posted a topic in UVM SystemVerilog DiscussionsAs used in the SystemVerilog LRM, 1800.1-2017.pdf, what is the difference between these two terms? The first seems well defined. The second, not so much. * time slot * time step Cliff Cummings/Sunburst Design wrote the following in CummingsSNUG2006Boston_SystemVerilog_Events.pdf: If that is correct, then it seems the term 'time step' has returned.
Reading in file + upsampling
sebs posted a topic in SystemC AMS (Analog/Mixed-Signal)I am currently working on a module that equidistantly reads in values from a text file. For this purpose, I use the file_in_tdf module from the basic library of COSIDE and have set the time step to 1s and interpolation to true. The idea now is to have a subsequent module that, however, has a lower time step, let's say 10 ms. Unfortunately I get the following error when trying to simulate: Inconsistency in timestep assignment between module: top. ... .i_file_in_tdf1 timestep: 1 s (1 Hz) expect: 10 ms (100 Hz) and module: top. ... .dummy_inst T: 10 ms (100 Hz) or expect: 1 s (1 Hz) rate1/rate2= 1/1 dT: -990 ms Of course both elements do not have the same time step, but I would expect that the file_in_tdf module is able to provide interpolated values every 10ms. So, is there any additional configuration I have to consider for the file_in_tdf module to have some kind of upsampling? Do I have to add a user-defined module in between which does the job for me or is such a timing setup simply not possible? Kind regards, Sebastian Simon