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time slot vs. time step (1800.1-2017.pdf)
ljepson74 posted a topic in UVM SystemVerilog DiscussionsAs used in the SystemVerilog LRM, 1800.1-2017.pdf, what is the difference between these two terms? The first seems well defined. The second, not so much. * time slot * time step Cliff Cummings/Sunburst Design wrote the following in CummingsSNUG2006Boston_SystemVerilog_Events.pdf: If that is correct, then it seems the term 'time step' has returned.