Jump to content

Search the Community

Showing results for tags 'tdf'.

More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV)
    • SystemC CCI (Configuration, Control & Inspection)
    • SystemC Datatypes
  • UVM (Universal Verification Methodology)
    • UVM 2017 - Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • UVM Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM (Pre-IEEE) Methodology and BCL Forum
    • UVM 1.2 Public Review
  • Portable Stimulus
    • Portable Stimulus 1.0
    • Portable Stimulus Pre-Release Discussion
  • IP Security
    • IP Security Assurance Whitepaper Discussion
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • Commercial Announcements
    • Announcements


  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL












Found 3 results

  1. Hi again! Maybe this is too obvious, but I've been wonderin for a while now and never found the answer (and dared to ask for it ). Is it possible to directly pass whatever comes from an tdf_in port to a tdf_out port? Not only that, is it possible to do it in a sc_module instead of a sca_module? For a better explanation I'll leave a piece of code. Let's say I have: #include <systemc-ams> class some_module : public sc_core::sc_module { public: sca_tdf::sca_in<int> in; sca_tdf::sca_out<int> out; some_module(sc_core::sc_module_name nm); }; Until now I was adding an object, let's call it "tdf_some": #include <systemc-ams> class tdf_some_module : public sca_tdf::sca_module { public: sca_tdf::sca_in<int> in; sca_tdf::sca_out<int> out; tdf_some_module(sc_core::sc_module_name nm) {} void processing() { out.write( in.read() ); } }; Then, in the previous class I would change to: #include <systemc-ams> class some_module : public sc_core::sc_module { public: sca_tdf::sca_in<int> in; sca_tdf::sca_out<int> out; // Add new TDF module tdf_some *ts; some_module(sc_core::sc_module_name nm) { // Instantiate and bind ports ts = new tdf_some("ts"); ts->in(in); ts->out(out); } }; Looks like a very simple question (and I hope so), but I still haven't been able to solve it. Any ideas? Thanks
  2. Hi all! I have an error that I never had before with AMS. I have a few sc_modules with in and out TDF ports. Inside these sc_modules I have sca_modules, which are connected to those in and out TDF ports. This have been working fine until now, but I created a new class of module exactly the same way as the others and I have this error. I checked in the library and it seems like my sca_module is not assigned to any view: if (view_interface == NULL) { std::ostringstream str; str << "Error: " << name() << " a sca_module must be associated with a concrete view!" << std::endl; str << "It is not allowed to instantiate the sca_module base class." << std::endl; SC_REPORT_ERROR("SystemC-AMS",str.str().c_str()); } I know that maybe it not clear. I can give more details. But I am totally lost with this. Any ideas? Thanks
  3. Hi everyone, I have been working with SystemC-AMS lately and having nice results, but now I'm facing some issues with the sca_eln::sca_tdf::sca_vsink module. I created some sc_modules with ELN modules inside. Quite briefly, the final electrical network (which I get from putting those sc_modules together) that I have been having problems with is: ELN: node_ref -> vsource -> node -> vsink -> node -> r -> node -> vsink -> node -> r -> node_ref SC :|-----GENERATOR-----|->|-----------PIPE-----------|->|----------PIPE------------| -> |---SINK---| If understood correctly the sca_eln::sca_tdf::sca_isink module is like a voltage source with v = 0 V, so they should not be connected in parallel. I do not know if the vsink works in a similar way, being a current source, so there should not be two connected in a row. Taking a look at the Users guide it is noted for both modules that "No equation added to the equation system", so I'm not sure if this is a conflict because of what I just mentioned. The error I'm getting is: I would like to know the reason why this is not working, if anyone happen to find any The idea of having vsink's there is because I want to send the value from the electrical network in that spot to a TDF module. I'm not sure if this is ok or is a crazy idea. I hope I explained everything clearly, otherwise, just ask and I'll try to do it better Thanks a lot! Kike
  • Create New...