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Showing results for tags 'systemc/tlm'.
Found 3 results
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Hi all, I was trying something different and came across a issue which looks odd to me. I have a main function and from there I am calling sc_main(). In sc_main, I am starting and ending simulation < sc_start, sc_stop >. something like Example : int main(){ sc_main() //gives the expected output sc_main() // creashes Error: insert module failed: elaboration done return 0 } I am expecting that my simulation should run 2 times. But, I am facing " ERROR- insert module failed: elaboration done " while calling 2nd sc_main. ---Its see
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Hello everyone, this is my first post. Hope you are all well. I work for a major US car manufacturer in Silicon Valley. I am organizing an internal workshop on a general topic of modeling and simulation for pre-silicon SW development. I want to bring my audience to a common understanding of Virtual Platforms based upon SystemC\TLM. The workshop will be held in San Jose', CA at the end of September. I would prefer someone (1) Who's local as we don't have budget for travel expenses, but we can pay an honorary fee for the speech (2) who's not affiliated with any tool vendor as we don't need a s
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Hi, To create a dynamic process we have to use sc_spawn function, I want to know if it is possible to create a dynamic port ? else, how we can create a dynamic communication path between two components ? Thanks Ted
