Jump to content

Search the Community

Showing results for tags 'systemc/tlm'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV)
    • SystemC CCI (Configuration, Control & Inspection)
    • SystemC Datatypes
  • UVM (Universal Verification Methodology)
    • UVM 2017 - Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • UVM Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM (Pre-IEEE) Methodology and BCL Forum
    • UVM 1.2 Public Review
  • Portable Stimulus
    • Portable Stimulus 1.0
    • Portable Stimulus Pre-Release Discussion
  • IP Security
    • IP Security Assurance Whitepaper Discussion
  • IP-XACT
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • Commercial Announcements
    • Announcements

Categories

  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests


Biography


Location


Interests


Occupation


Company

Found 3 results

  1. Hi all, I was trying something different and came across a issue which looks odd to me. I have a main function and from there I am calling sc_main(). In sc_main, I am starting and ending simulation < sc_start, sc_stop >. something like Example : int main(){ sc_main() //gives the expected output sc_main() // creashes Error: insert module failed: elaboration done return 0 } I am expecting that my simulation should run 2 times. But, I am facing " ERROR- insert module failed: elaboration done " while calling 2nd sc_main. ---Its seems like the old simulation is itself not getting cleared---- As after doing sc_stop the simulation should stops and clears all memories, then I believe it should have worked. --Can any help me to make this done, if possible-- Any hint will be very helpful for me. Thanks in advance :). Best Regards, Nitin
  2. Hello everyone, this is my first post. Hope you are all well. I work for a major US car manufacturer in Silicon Valley. I am organizing an internal workshop on a general topic of modeling and simulation for pre-silicon SW development. I want to bring my audience to a common understanding of Virtual Platforms based upon SystemC\TLM. The workshop will be held in San Jose', CA at the end of September. I would prefer someone (1) Who's local as we don't have budget for travel expenses, but we can pay an honorary fee for the speech (2) who's not affiliated with any tool vendor as we don't need a sales pitch. The speech should be focused on a explanation of the SystemC\TLM technology and how it can be used to create Virtual Platforms for embedded SW development (we are not interesting in learning, at least for now, on how to create a SystemC model), followed by industrial experiences in deploying it in large companies with legacy development processes for embedded SW (including SW integration and testing). Then a Q & A would follow. I would expect the speech/presentation to take 1 hr or 90 mins tops including Q & A. If interested or know some one that would fit the profile, please reply to this thread and then we can take it from here. Thanks for your attention. Paolo
  3. Hi, To create a dynamic process we have to use sc_spawn function, I want to know if it is possible to create a dynamic port ? else, how we can create a dynamic communication path between two components ? Thanks Ted
×
×
  • Create New...