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Showing results for tags 'system verilog'.
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Hi, The purpose of this discussion is to understand different possibilities by which the simulation performance, memory usage can be increased. Scoreboard as we understand needs the data/packets/frames etc to be stored/buffered to do a comparison with the actual data out. This works out fine when we have small sized array ranging from few bytes to few thousands of bytes.. However imagine, if we have 100 thousands of bytes and above and there is a need to store them and lets say multiple of such lanes/flows , then this would take a hit on the simulation performance. And this gets worse if we have to reuse and port it to a subsytem/chip level simulations.. With this as the background, i am looking at alternate approach for scoreboards.. In a way is possible avoid scoreboard and check the data as it comes without the need to store the expected/input data. Approach that can be thought of : 1. Generating incremental data pattern and check at the output .. (Comes again with issues like aliasing etc.. and hence need to have longer patterns.) 2. Generation of PRBS stream as the payload of the frame.. and then have a PRBS checker at the output.. and see it remains locked.. (Debug would get worse with this.. if there is a mismatch) 3. Having a byte scoreboard.. something like that.. (Not sure how feasible this is). There are many challenges even with these approach.. I am just wondering if someone has already experienced such cases and what kind of challenges are thrown out.. Appreciate any input on this. Regards, svuvmuser !
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Hello, I am developing a verification environment for a DUT that has cache memory in it. I would like to model that memory in my environment and make it accessible to various components at different levels of hierarchy. What is the best way to add "hooks" for the same? This is what my env looks like. class top_env extends ovm_env; `ovm_component_utils(top_env) mem_model mem_model_h; scoreboard scoreboard_h; checker checker_h; endclass I want the mem_model to be accessible to all the components in the design at any given time. I tried using set_config_object/get_config_object set_config_object("*", "mem_model_h", mem_model_h, 0); but I guess for that to work my memory model class needs to be derived from the ovm_object class. I am not sure at this point if I will be needing other functions provided by ovm_component class hence I am not sure if that is the solution. I guess I am looking for one of the two things, 1. Passing the handle to this mem_model to all components in the hierarchy. 2. Instantiate the mem model outside of the env and have it provide some helper functions similar to friend functions in C which can then be used by thr other components. Also my env is based in OVM so I am looking for only OVM based solutions. Appreciate any response. Thanks. -
For AXI write transaction axi wready signal determines whether the slave can accept the data. For write burst performance i need to capture the latency between "WREADY" and "next WREADY" signal. For example this ready signal is getting low at clockno 8 and it should remain low for clockno 9 and 10 and the clockno 11 the signal will be high as per the slave configuration. when the multiple burst transacion occurs with (write length > 2) the ready signal behavior will be like above. I want to write a functional coverage like "wready" and next "wready" signal latency is 2 which means when the ready signal is low it will low for 2 clk cycles and then ready will high(if there are multiple write burst transaction).
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Which is best method to start , randomize and end the sequence among the `uvm_do, start_item, `uvm_create, `uvm_send and the others and why? Please explain.
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Hi all, What exactly is the difference between uvm_hdl_force and uvm_hdl_deposit? The UVM Class reference document doesn't provide much explanation. Please help. Thanks, Shreyas
