Jump to content

Search the Community

Showing results for tags 'sc_main'.

More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV)
    • SystemC CCI (Configuration, Control & Inspection)
    • SystemC Datatypes
  • UVM (Universal Verification Methodology)
    • UVM 2017 - Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • UVM Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM (Pre-IEEE) Methodology and BCL Forum
    • UVM 1.2 Public Review
  • Portable Stimulus
    • Portable Stimulus 1.0
    • Portable Stimulus Pre-Release Discussion
  • IP Security
    • IP Security Assurance Whitepaper Discussion
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • Commercial Announcements
    • Announcements


  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL












Found 2 results

  1. I am new to SystemC, and this is my first program. I have timer module already built. sc_main should contain the following points: Instantiation of timer module Trace ports/variable: clock start timeout count start signal to create a trace which contains a waveform of exactly 30 cycles (300ns, that is.) This 30-cycle waveform should include following scenarios: reset the timer for 3 cycles before it is released for counting, during counting reset the timer before count reaches 0, and during counting reset the timer after count reaches 0 clock frequency: 100MHZ Could anyone tell me how to improve my sc_main to get the desired output? Thanks in advance code files timer.h #include "systemc.h" SC_MODULE(timer) { sc_in<bool> start; // ports sc_out<bool> timeout; sc_in<bool> clock; int count; // data and function members void runtimer(); SC_CTOR(timer) { // constructor SC_THREAD(runtimer); sensitive << clock.pos() // sensitivity list << start; count = 0; } }; timer.cpp // timer.cpp #include "timer.h" void timer::runtimer() { while(1) { if (start.read()) { cout << "Timer: timer start detected "<< endl; count = 5; timeout.write(0); } else { if (count == 0) timeout.write(1); else { count--; timeout.write(0); } } wait(); } } main.cpp // main.cpp #include "systemc.h" #include "timer.h" int sc_main(int argc, char* argv[]) { sc_signal<bool> TIMEOUT, START, COUNT; sc_time clkPrd(10, SC_NS);// period sc_clock CLOCK("clock", clkPrd, 0.50, SC_ZERO_TIME, true); // timer clock // Binding timer tm("timer"); tm.count = COUNT; tm.timeout(TIMEOUT); tm.start(START); tm.clock(CLOCK); // sensitivity list tm << START << TIMEOUT << CLOCK; // tracing: sc_trace_file *tf = sc_create_vcd_trace_file("RESULT.vcd"); // External signals sc_trace(tf, CLOCK, "clock"); sc_trace(tf, START, "start"); sc_trace(tf, TIMEOUT, "timeout"); sc_trace(tf, COUNT, "count"); sc_start(30*clkPrd); // simulate for 30 cycles s sc_close_vcd_trace_file(tf); return(0); } Desired waveform output is attached.
  2. I have got an error when I was running a test. My bench has been constructed by system C on cadence incisive 14.20. The run command is like this: irun -sysc -uvmtop "SC:top" -top dut -f list.f -DTV_PATH=\\\"/home/test0/\\\" In sc_main.cpp, there is a line like this: cout << "TV_PATH: " << TV_PATH <<endl; But when I was running, there is a compile error like this: line 12: error: expected an expression cout << "TV_PATH: " << TV_PATH <<endl; extra text after expected end of number cout << "TV_PATH: " << TV_PATH <<endl; Hi nice guys, How can I solve this problem? Thanks!
  • Create New...