Jump to content

Search the Community

Showing results for tags 'sc_lv'.

  • Search By Tags

    Type tags separated by commas.

  • Search By Author

Content Type


Forums

  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV)
    • SystemC CCI (Configuration, Control & Inspection)
    • SystemC Datatypes
  • UVM (Universal Verification Methodology)
    • UVM (IEEE 1800.2) - Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • UVM Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM (Pre-IEEE) Methodology and BCL Forum
  • Portable Stimulus
    • Portable Stimulus Discussion
    • Portable Stimulus 2.0 Public Review Feedback
  • IP Security
    • SA-EDI Standard Discussion
    • IP Security Assurance Whitepaper Discussion
  • IP-XACT
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • Commercial Announcements
    • Announcements

Categories

  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption

Calendars

  • Community Calendar

Find results in...

Find results that contain...


Date Created

  • Start

    End

Last Updated

  • Start

    End

Filter by number of...

Joined

  • Start

    End

Group

AIM

MSN

Website URL

ICQ

Yahoo

Jabber

Skype

Location

Interests

Biography

Location

Interests

Occupation

Company

Found 3 results

  1. Hossam
    Hi, I have a simple project it's goal is to create a 32 bit ripple adder from an array of Full adders (FA). I have successfully implemented the FA (implementation attached) , but I have a simple problem now. Unlike the FA , the Ripple adder has many more inputs, and I cant find an efficient way to model these inputs , for instance in VHDL I would have an input port with the number of bits that I needed and I can access them easily in the architecture of the module, Unfortunatly this isn't the case for me in systemC. Approaches that I tried include: Using ( sc_in<sc_lv<
  2. Hossam
    Hi, I have a simple project it's goal is to create a 32 bit ripple adder from an array of Full adders (FA). I have successfully implemented the FA (implementation attached) , but I have a simple problem now. Unlike the FA , the Ripple adder has many more inputs, and I cant find an efficient way to model these inputs , for instance in VHDL I would have an input port with the number of bits that I needed and I can access them easily in the architecture of the module, Unfortunatly this isn't the case for me in systemC. Approaches that I tried include: Using ( sc_in<sc_lv<
  3. jenjel
    Hello, How can i plz define an sc_lv with a variable width ? Thank you for your help
×
×
  • Create New...