Jump to content

Search the Community

Showing results for tags 'sc_fifo'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV)
    • SystemC CCI (Configuration, Control & Inspection)
    • SystemC Datatypes
  • UVM (Universal Verification Methodology)
    • UVM (IEEE 1800.2) - Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • UVM Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM (Pre-IEEE) Methodology and BCL Forum
  • Portable Stimulus
    • Portable Stimulus Discussion
    • Portable Stimulus 2.0 Public Review Feedback
  • IP Security
    • SA-EDI Standard Discussion
    • IP Security Assurance Whitepaper Discussion
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • Commercial Announcements
    • Announcements


  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL












Found 9 results

  1. hi, I am trying to simulate a TLM Design in systemc. On simulation I get following errors in sc_fifo.h files. C:/Xilinx/Vivado_HLS/2015.4/win64/tools/systemc/include/sysc/communication/sc_fifo.h:314:13: error: no match for 'operator<<' in 'os << *(((com*)((const sc_core::sc_fifo<com>*)this)->sc_core::sc_fifo<com>::m_buf) + ((unsigned int)(((unsigned int)i) * 20u)))' C:/Xilinx/Vivado_HLS/2015.4/win64/tools/systemc/include/sysc/communication/sc_fifo.h:314:13: note: candidates are: c:\xilinx\vivado_hls\2015.4\msys\bin\../lib/gcc/mingw32/4.6.2/include/c++/o
  2. Dear Sir, I am new to SystemC. Pl. advise how to access ex1[0] etc. in the following program: #include "systemc.h" #include <stdio.h> SC_MODULE(exfifo) { SC_CTOR(exfifo) { SC_METHOD(fifo_pop); sc_fifo<int> packet_fifo(5); } void fifo_pop(void) { int val; if ((ex1[0].packet_fifo).nbread(val)) cout << "\n hi \n"; WAIT(2, SC_NS); }   };     int sc_main(int argc, char* argv[]) { cout << "Maha Ganapatim Veera Nangai Gnanananda\n"; sc_vector<exf
  3. Hallo, i have been trying to change de defalut sc_fifo size, but i dosen´t work at all. main.cpp sc_fifo<ressource> ff_in_ch; // ressource si a self-defined data-type class X sc_fifo_out<ressource> ffin; class Y sc_fifo_in<ressource> ffin; How can i change the size of the sc_fifo? I have tried this: sc_fifo<ressource> ff_in_ch(64); but it dosen´t work at all. Thanks in adavanced!
  4. Hi all, I created two modules with interfaces as below: M1 : sc_port<sc_fifo_out_if<T>, 0> a M2 : sc_port<sc_fifo_in_if<T>, 0> a2; I have a third module which is also my top module i.e M3 and tried binding M1 output to M2 input to create a communication channel. I have tried using sc_fifo<T> but it doesn't work. How do I bind M1 output to M2 input inside M3 module? Please not that T is a struct. Thanks
  5. Hi everyone, I'm met some problem. In box below you can see my code. struct Some_stuct { int data; float data_f; }; class payload_t { public: unsigned char *data; unsigned lenght; inline friend ostream& operator << ( ostream& os, payload_t const & v ) { os << "(" << v.data << "," << std::boolalpha << "," << v.lenght << ")"; return os; } }; SC_MODULE(tx) { sc_port<sc_fifo_out_if<payload_t> > out_port; void process() { Some_stuct data; payload_t out_data; while(true) { data.data = 5;
  6. Hi all, I am defining the sc_fifo as, sc_fifo<sc_lv<FLIT_SIZE> > fifo_rx1 (BUFFER_SIZE); and BUFFER_SIZE and FLIT_SIZE are defined in another header file as, const unsigned int FLIT_SIZE = 39; const int BUFFER_SIZE = 50; The problem I encounter is, whenever I change the BUFFER_SIZE, I do not get any change in the performance of my system. And I checked that sc_fifo is getting defined at default size of 16 (with num_free() ). As I understand the size_ variable in sc_fifo class is of int type, so I am not sure what is the problem exactly, Help is appreciated. Thank you. Si
  7. Hello All, I have a question about determining the source of event for a module (module_a) connected to multiple modules (module_b1, module_b2, and module_b3) through sc_fifos (sf_b1_to_a, sf_b2_to_a, and sf_b3_to_a). module_a has a process that processes both clocked and non-clocked events. I use clk.posedge() to determine the source of clocked and non-clocked events. The process in module_a is made sensitive to clk.pos(), sf_b1_to_a.data_written(), sf_b2_to_a.data_written(), and sf_b3_to_a.data_written(). The problem is when the module_a process is triggered due to one of the non-clocked
  8. Hell All, I posted a question entitled "Determining source of events using global fifo" on Sep 9, 2013. Surprisingly, I have not got a reply for this post so far. What is wrong with this post? Any idea? Can anyone see my post? Thanks, Alireza
  9. Hello Everyone, I am a beginner at systemc. I am interested in sc_fifo channel and investigated the OSCI simulator source code. I found sc_fifo has a member function named "data_written_event" and its prototype is like below: virtual const sc_event& data_written_event() const; I want to get a callback/notify when a specific sc_fifo channel is written or read. My solution is: - Preface I used the sc_get_top_level_objects() and get_child_objects() to iterate out all the sc_object. (This is the way I get the sc_fifo object) - Make a callback/sensitive by user code 1. Try to
  • Create New...