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Found 1 result

  1. judith_113
    Hi UVM experts, I am working on a testbench to verify register behavior and came a cross an issue with W0CRS register fields with reset value of 1. Please correct me if i am wrong here. A 3-bit register field of type W0CRS with default value 3'b101. W0CRS states "W: 1/0 no effect on/clears matching bit, R: sets all bits" tx_byte_bus.configure(this, 3, 0, "W0CRS", 0, `UVM_REG_DATA_WIDTH'h00000005, 1, 1, 1); and my testcase does the following transactions to verify the register: after system reset and regModel.reset (reset all mirrored values to their default) -> write all 1's -> then followed by a read -> then followed by a 2nd read I expected the first read return 3'b101 as W0CRS shouldn't change m_value after write-all-1's is done, but the test failed with an uvm_error complaining the mirrored value is 3'b000, not match DUT value 3'b101. - if I update the default value to all 0's in both DUT and UVM_REG file, then test passed - if I udpate the default value to all 1's in both DUT and UVM_REG file, then test failed with the same error. Is this a bug with W0CRS register? thanks, Judy
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