Jump to content

Search the Community

Showing results for tags 'ports'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV)
    • SystemC CCI (Configuration, Control & Inspection)
    • SystemC Datatypes
  • UVM (Universal Verification Methodology)
    • UVM (IEEE 1800.2) - Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • UVM Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM (Pre-IEEE) Methodology and BCL Forum
  • Portable Stimulus
    • Portable Stimulus Discussion
    • Portable Stimulus 2.0 Public Review Feedback
  • IP Security
    • SA-EDI Standard Discussion
    • IP Security Assurance Whitepaper Discussion
  • IP-XACT
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • Commercial Announcements
    • Announcements

Categories

  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests


Biography


Location


Interests


Occupation


Company

Found 3 results

  1. Hi, I am dynamically populating a network of SC_MODULES inside a global modele `net`. As soon as I create a module `x`, I bind all ports to x (say `a` and `b`) to `sc_signal` x.a and x.b in `net`. When I simulate, all SC_MODULEs run independently and I can see values of `sc_signal`s changing when port value changes. So far so good! This has the advantage and end-user does not have to bind all the ports (many of them are really not essential). Now I wish to connect port `a` and `b` of module `x` to port of `m` and `n` of module `y`. Any new binding will raise an error since I am allo
  2. Hi, I have a question in how glue logics between two or more ports get represented in IPXACT. Lets say there is an ADHOC Connection between, PORT A of instance A and PORT B of instance B, in such a way that, PORTB is connected as 32'habcd ^ PORTA Like, Instance A: output port A Instance B: input port B Now, on Top file, In SV , I have following glue logic. module Top module A instance A( .A(A) ) module B instance B( .B(32'habcd ^ A) //32'habcd XOR with A ) endmodule Now, in adHoc connection,we genrally, represent two conne
  3. Hi, I have two files. In header file I have two modules `camkii` and `camkii_ring`. The `camkii_ring` contains N number of `camkii` submodule. I thought of using std::vector to instantiate the submodules. See the code below. #ifndef CAMKII_H #define CAMKII_H #include <systemc.h> #include <vector> using namespace std; SC_MODULE(camkii) { sc_in_clk clock; sc_in<double> ca_conc_in; sc_signal<double> v1, v2, v3; void init() { cout << "[Ca] " << ca_conc_in << endl; //cout << sc_get_time_reso
×
×
  • Create New...