Jump to content

Search the Community

Showing results for tags 'port binding'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV, CRAVE, FC4SC)
    • SystemC CCI (Configuration, Control & Inspection)
    • SystemC Datatypes
  • UVM (Universal Verification Methodology)
    • UVM (IEEE 1800.2) - Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • UVM Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM (Pre-IEEE) Methodology and BCL Forum
  • Portable Stimulus
    • Portable Stimulus Discussion
    • Portable Stimulus 2.0 Public Review Feedback
  • IP Security
    • SA-EDI Standard Discussion
    • IP Security Assurance Whitepaper Discussion
    • IP-XACT Discussion
  • SystemRDL
    • SystemRDL Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • Commercial Announcements
    • Announcements


  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption


  • Community Calendar

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL












Found 3 results

  1. Hello, I am currently working on a model that consists of three components: memory, adder and link element between the two of them. The data transmission between them happens via ports that look like sc_in<BasePort*>, so a pointer to the BasePort class. This class only contains the status bits (e.g. valid), while the actual data is part of a child class of BasePort that is just callled Port. Inside the memory an object of type Port will be instatiated, the data will be written to that object, and finally the oject is static casted to an object of type BasePort that will then be written to the output port. The reason for this split is that the linking element should be able to work independently from the underlying data type that is transmitted. The problem I am running into is that the data of BasePort, the status bits, seem to get lost during transmission. So for example, in the linking element I can only see the data while the valid flag will always be set to false, even though it was correctly set in the memory. So, i can see the correct data but the valid flag will not be set. So far I have checked that the pointer that is seen in the linking element is the same as the one that is written in the memory, which is the case. I have also tried chaning the data type of the channels connecting the components from sc_signal<BasePort*> to sc_buffer<BasePort*> but that also didn't fix the issue. I really don't understand why this part of the data transmission is lost. If either all or nothing is lost that would make sense, but I can't think of any reason why only the data of BasePort but not the data of Port is lost. Any thoughts on what I am doing wrong here? Thank you!
  2. Hi guys I'm working on a simulation system that the connection between components changes during the execution of the system. First time I'm facing this issue and not quite sure if I can change module to module connections during run-time and dynamically. Any thoughts how I can do this in SystemC? Thanks
  3. Hello Experts, presently I am designing a simple A2D converter in SystemC-AMS. While compiling complier returns with some errors. I would be very thankful to you, if you could comment on the errors messages. // A2D.h #include <systemc-ams> #include <systemc> #include <stdio.h> using namespace std; SCA_TDF_MODULE (a2d_nbit) { //port declaration sca_tdf::sca_in<double> a_in; // analog input pin sca_tdf::sca_de::sca_in<sc_dt::sc_logic> start; //start signal sca_tdf::sca_de::sca_in<sc_dt::sc_logic> clk; //clock signal sca_tdf::sca_de::sca_out<sc_dt::sc_logic> eoc; //end of conversion pin sca_tdf::sca_de::sca_out< sc_dt::sc_lv<8> > d_out; // digital output signal a2d_nbit(sc_core::sc_module_name nm, double Vmax_ = 5.0, double delay_ = 10.0e-6, int bit_rng = 8): a_in("a_in"), start("start"),clk("clk"), eoc("eoc"), d_out("d_out"), Vmax(Vmax_), delay(delay_), bit_range(bit_rng){} void set_attribute() { set_timestep(10.0, sc_core::SC_US); eoc.set_delay(0); } void initialize() { //eoc.initialize(sc_dt::SC_LOGIC_0); } void processing(); private: double Vmax; // ADC maximum range double delay; // ADC conversion time int bit_range; //vector length of d_temp and d_out }; //A2D.cpp has got only processing function defined. //A2D_top_level.cpp #include<systemc-ams.h> #include<systemc.h> #include<A2D.h> #include<vtg_src.h> using namespace std; using namespace sc_core; SC_MODULE (A2D_top_level) { a2d_nbit a2d; vtg_src input_vtg; sc_clock clk1("clk1", 100, SC_US,0.5, true); void start_logic(){ while(true) { start.write(sc_dt::SC_LOGIC_0); wait(2, sc_core::SC_MS); start.write(sc_dt::SC_LOGIC_1); wait(2, sc_core::SC_MS); start.write(sc_dt::SC_LOGIC_0); sc_core::sc_stop(); } } A2D_top_level(sc_core::sc_module_name nm): in("in"), out("out"), a2d("a2d"), input_vtg("input_vtg"),clk1("clk1"), start("start"), clk("clk"), eoc("eoc") { input_vtg.out(in); clk(clk1.signal()); a2d.a_in(in); a2d.start(start); a2d.clk(clk); a2d.eoc(eoc); // a2d.d_out(out); SC_THREAD(start_logic); } private: sca_tdf::sca_signal <double> in; sc_core::sc_signal<sc_dt::sc_lv<8> > out; sc_core::sc_signal<sc_dt::sc_logic> start, clk, eoc; }; compiler returns with following errors !!! A2D_top_level.cpp:13: error: expected identifier before string constant A2D_top_level.cpp:13: error: expected ‘,’ or ‘...’ before string constant A2D_top_level.cpp: In constructor ‘A2D_top_level::A2D_top_level(sc_core::sc_module_name)’: A2D_top_level.cpp:29: error: class ‘A2D_top_level’ does not have any field named ‘clk1’ A2D_top_level.cpp:33: error: ‘((A2D_top_level*)this)->A2D_top_level::clk1’ does not have class type A2D_top_level.cpp:41: error: ‘SC_CURRENT_USER_MODULE’ has not been declared please let me know your views. thanks in advance. Milind.
  • Create New...