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Showing results for tags 'named event'.
We (as an industry) normally use virtual interfaces to communicate between the module 'world' and the class 'world' of SystemVerilog. Right?** Can anyone comment on the use of events (named events) for class<-->module communication? Good? Bad? Gothchas? Scenario: A test wants to send a signal (trigger) to the top (where the DUT is instantiated). Creating a 1b interface to transmit this trigger seems like overkill, but that is what I did. I had some trouble triggering on an event between module and class. Hierarchy problems. I did not try passing the event thru the config_db - if that even makes sense (is possible). **Correct me if I'm wrong, but that's the way I see it. I'm sure the UVM base class has a sea of code that I don't understand.