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Found 2 results

  1. SumitK
    Hi Folks In my inteconnect model, I have a target socket In (which allows multiple initiator sockets connected to it) and an array of initiator socket like folloiwng tlm_utils::multi_passthrough_target_socket<QC_Mux_base<N_TARGETS>, 32, tlm::tlm_base_protocol_types,0,sc_core::SC_ZERO_OR_MORE_BOUND > In tlm_utils::multi_passthrough_initiator_socket<QC_Mux_base<N_TARGETS>, 32, tlm::tlm_base_protocol_types,1,sc_core::SC_ZERO_OR_MORE_BOUND > Out[MAX] Now if I receive some backward transaction, e.g. nb_transport_bw or invalidate_direct_mem_ptr, on some o
  2. SumitK
    Hi Folks Is it allowed to connect an initiator port to a target port up in the hierarchy ? Is it allowed to connect an target port to a initiator port up in the hierarchy ? I assume no but what I observe that OSCI systemc implementation allows this. I tried to reproduce this problem with a small example(attached) where I have a component model with following ports tlm_utils::multi_passthrough_initiator_socket<model,32, tlm::tlm_base_protocol_types,0,SC_ZERO_OR_MORE_BOUND> master; tlm_utils::multi_passthrough_target_socket<model,32, tlm::tlm_base_protocol_ty
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