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Showing results for tags 'module'.
Found 3 results
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Using VCS, I can compile and run multiple top-level modules. In the example I am running, I have a dut module and a bind-file module. The bind-file module is nothing more than: module bindfiles; bind dut pLib_dut p1 (.*); endmodule When I compile and run, I indeed see both top modules have been compiled: Top Level Modules: bindfiles dut And both run just fine as expected. Now the question: If I compile both top modules, can I run simv with just the dut module and ignore the bindfiles module? I would like to simulate both with the bindfiles and without th -
Hello everyone, I have a folder with many modules. I want to create a configuration file specifying which of those modules to use in my simulation. In the sc_main.cpp, before the simulation starts I would like to open my configuration file, read which modules I would like to open and then create instances, connect their ports etc The configuration file contains all the necessary information as number of ports, type of each port , name of the module, name of the file etc. I can easily create the signals I need but I don't know how I can create the module instance. example of con
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Two modules, an input Generator and a Controller. The Generator sends a signal to increase a value in the Controller. The controller contains a loop where it checks if this value is > 0 and in that case do some stuf and reset it to zero.; How should I connect these two modules? Sending an event seemed most intuitional, but it doesnt look like the standard way to do this. I also read about semaphore but I'm not sure how to connect them. (I also want a monitor module to be able to print the value at some points (probably when it is reset))
