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Found 1 result

  1. mrforever
    Hi, experts, There is several drivers and one subscriber. I put one uvm_analysis_port in each driver and several imps in the subscriber via using macro `uvm_analysis_imp_decl(_a), `uvm_analysis_imp_decl(_b, etc. Also Implement functions write_a(), write_b(), etc. write_a() and write_b() have different processing logic. Then, the uvm_analysis_port in each driver invokes one of the functions write_a(), write_b(), etc. But the VCS reports such an error: Could not find member 'write_a' in class 'uvm_analysis_port', at "/EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/tlm1/uvm_analysis_port.svh", Is there anybody to handle my problem? Thanks in advance!
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