Jump to content

Search the Community

Showing results for tags 'hls'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV, CRAVE, FC4SC)
    • SystemC CCI (Configuration, Control & Inspection)
    • SystemC Datatypes
  • UVM (Universal Verification Methodology)
    • UVM (IEEE 1800.2) - Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • UVM Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM (Pre-IEEE) Methodology and BCL Forum
  • Portable Stimulus
    • Portable Stimulus Discussion
    • Portable Stimulus 2.0 Public Review Feedback
  • IP Security
    • SA-EDI Standard Discussion
    • IP Security Assurance Whitepaper Discussion
    • IP-XACT Discussion
  • SystemRDL
    • SystemRDL Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • Commercial Announcements
    • Announcements


  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption


  • Community Calendar

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL












Found 4 results

  1. Hello everyone, i am very new to both systemc and HLS. I have systemc code that I am trying to synthesize using Vivado HLS 2019.2 (since it still supports Systemc). The systemc code works fine but was not originally written for Synthesis and I am trying to make it synthesizable. I have a problem since the source code has arrays of ports for example: sc_in<sc_int<8>> input [10]; sc_out<sc_int<8>> output[10]; that are connected to arrays of signals, example: sc_signal<sc_int<8>> sig[10]; What is the best way to making the code synthesizable? I tried pragmas but the arrays are defined in the SC_Module in the header files and not inside functions, I believe this is causing the following error: ERROR: [HLS 200-70] '#pragma HLS ARRAY_PARTITION variable=input type=complete dim=0' is not a valid pragma I also tested using sc_in<sc_lv<80>> input , however I am not sure of connecting the port to a signal array since using input.read().range(0,8)(sig[0]); is causing errors and also i am not sure how to connect sc_out with another sc_out when using sc_lv. Thanks in advance for your help!!
  2. Hello everybody, I was looking for a main topic about synthesizable SystemC here but there is not any one specific about it. I have been learning and working with SystemC to RTL, mostly modelling pure digital systems and trying to do it clock cycle accurate. The last project that I am working on is on model and implement a 32bit processor core. Until now the pure SystemC model is fulfilling the specifications and now I am trying to synthesize it with VIVADO HLS suite. I already checked Accellera Synthesis Subset 1.4.7 and many other kind of manuals or guidelines for that purpose. I am using SC_SIGNAL as channel between methods inside the same module I have the sc_signal defined as: sc_core::sc_signal<sc_dt::sc_bv<32> > register[32] and it is added to the sensitivity list in the following way: SC_METHOD(prc_assign_rf_reg); sensitive << register[0]; sensitive << register[1]; .... down to sensitive << register[32]; My question is somebody knows or have in mind some other way to implement the sensitivity list of this multidimensional signal array or could advice me another way to implemented, in order to firstly avoid to instance every array row position in the sensitivity list and secondly to implement this type of vector memory in another way. Thanks for your attention and support. Juan
  3. Hi everyone, As part of my job I try to implement a FFT function in my ZedBoard. I found some example including one in the SystemC folder unfortunately not synthesizable. Furthermore, I use a free version of Vivado HLS and this tool is very restrictive (few things are synthesizable). So, I will going to have to code my own version of this function (8k/16k/32k FFT). For doing this, I started by cut the FFT's mathematical formula and try to code a exponential function. I realized I can't use the "math.h" library and then I have to code all with only logic gates. At this level, I prefer to code directly in VHDL. Does anyone have a experience with this synthesis tool and can give me a simpler way to achieve my goal ? Maybe I see the problem of the wrong angle. Best regards
  4. Hi all, I'm quite new to all the SystemC world. As far as I got the sc_fixed type should be synthesizable. My problem at the moment is that I have a number, and I need the negative version of that number. The easiest way to do it is to multiply for -1. The problem is the HLS. I actually don't know how this it will be handled by the tool. I would like to avoid to instantiate a multiplier just to do a simple 2 complement operation ( flip the bits and adding 1 to the LSB ). If I can't trust the HLS tools I guess the safest way would be to do the 2 complement by myself, but even there I have some concern : sc_fixed <8,3,SC_RND,SC_SAT> foo, foo_neg; foo_neg = ~foo + 2^(8-3) ( PSEUDOCODE : I still need to figure out ) I don't really like to add 2^-5, it isn't clean. Even here probably it's easier to convert in int and add 1, but still it's quite messy in my opinion. Does anyone know if the tools are smart enough to handle correctly a multiplication between sc_fixed type and -1 and to implement correctly the 2 complement operation? If not how should I need to proceed ?
  • Create New...