Search the Community
Showing results for tags 'hdl_path'.
Found 1 result
-
Hi, In rtl design, I have a wire [3:0] d signal. It's assigned with 4 signals declared as reg type. So my question is when I try to add hdl path slice for d what should I do? I tried to add each of the four signals as slices, then in the test backdoor write to d has problem, I can't seem to pass wdata well. Ex: env. rm. d. write(...UVM_BACKDOOR) doesn't work. The d is a register naming which I create a uvm reg for it. Any input is appreciated.