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Hello All, I have some doubts related to the relationship between PSEL and PENABLE signals in the APB Protocol. The specification informs that: The PENABLE signal is asserted the following clock after PSEL is asserted and de-asserted after a transfer takes place. I would like to understand about the following conditions: 1) Can PENABLE toggle while PSEL is de-asserted? 2) Can PENABLE be asserted in the IDLE and/or SETUP phase? 3) Can PSEL go log in to the SETUP phase? 4) What happens when PSEL is asserted high in the ACCESS phase and PENABLE is not de-asserted? Thanks
Previous versions of IPXACT has attributes, 'left' and 'right' inside internalPortReference element of adHocConnection in design IPXACT as shown in the following 4 lines of xml. <spirit:adHocConnection> <spirit:name>....</spirit:name> <spirit:internalPortReference spirit:ComponentRef = "..." spirit:PortRef=".." spirit:left="..." spirit:right="...."/> </spirit:adHocConnection> These attributes basically say that which vector range of port from one component is mapped to another (I assume) However, the same IPXACT with latest schema, while validation gives schema error stating, attribute right/left is not allowed. Even the latest xsd files available with accellera doesn't define these attributes.There must be some means how currently, these multibit adHocConnections are mapped between two components inside an IPXACT-design. What could be the solution for this?