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Found 8 results

  1. The below assertions check that gnt is not high for consecutive clk cycles. Q1: v1 vs. v2: Are there benefits or relevant differences between these styles. Q2: v2 vs. v3: Does the placement of delay matter? Besides for end of simulation termination. The questions are mainly about whether some style is better for the simulator, or there is some non-obvious situation I should consider. module top; bit clk, gnt; bit [19:0] gnt_a; initial begin gnt_a = 20'b0011001010_0000001101; #200 $finish; end assign gnt = gnt_a[19]; always clk = #5 ~clk; always
  2. Hello all, This is very basic question and I know its not possible, but still I need to put some delay or wait in start of simulation/end of elaboration. I will give you the background, In end of elaboration i an initializing the value to a pin, and that pin is quite required for reset vector address. In start of simulation I am opening my gdb, which which stop at my reset vector address, but it seems the gdb is not updating the reset vector value, so I need a small delay. Is it possible? Any suggestion will be very helpful :) Thanks and Regards, Nitin_s
  3. Hi all, is there any way to implement the intra assignment delay in systemC without using sc_event()? for example : in verilog we write out = #10 in1 + in2; // intra assignment delay. how would i implement the same in systemC? regards, jatin
  4. Hello, I need to port following code from Verilog to SystemC: assign #DELAY out = in; What is the best known method to do this in SystemC? Similar question on stackoverlow https://stackoverflow.com/questions/5566785/specifying-signal-delays-in-systemc-as-clause-after-in-vhdl
  5. Good day, I have a question regarding how to determine the appropriate delay value for the wait( ) function call. In the target b_transport callback, we can add delay to the simulation time by passing delay amount to the wait( ) function. In simulation that uses quantum and temporal decoupling that targets super fast instruction accurate simulation, the timing does not have to be very detail (loosely timed). With or without delay in the target callback function will not cause any functional inaccuracy and still we could produce the platform that can support firmware/software developmen
  6. I've run into the following issue using the built-in UVM register tests. The built-in UVM register tests (seem to) start R/W-ing immediately after top-level reset is released. This was fine, initially. See attached image "Capture". We now have some delay between the release of top-level reset and the actual reset going to the register block. This is resulting in a read occurring before reset to the rtl regblock is released, and causes the test to hang. See attached image "Capture2". Without modifying the built-in register tests/sequences, how would anyone suggest that we cleanly
  7. Hi all, i am trying to translate a simulink model to system c module. The simulink block is a source block where it generates random number in the range of [ 0 , 253 ] and with a explicit sample period( the block produces outputs and if appropriate, updates its internal state) of 9 ns, and the output of this block is given to the next block with a latency of 1 sample period. i tried to translate this block to a system c module as shown below: #include "systemc.h" #include <stdlib.h> //for srand(uint) and rand() SC_MODULE(RNG){ sc_in_clk clk; sc_out< sc_uint > o
  8. Hi All, while simulating A2D convertor, I got following problems. Compilation: No Error running .exe file returns the following error message: ----------------------------------------------------------------------------------------------------------------------------------------------------------------- Warning: SystemC-AMS: Initialization for tracing of: CLK failed set wave to 0 In file: sca_trace_object_data.cpp:136 In process: method_p_0 @ 0 s Error: SystemC-AMS: Sample id (0) is greater than delay (0 while initializing port: A2D_dut.a2d.eoc In file: /home/4all/pac
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