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Showing results for tags 'create'.
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CodingStyle: handle name vs create's string name. To match or not to match? What pros, cons, or team rules can you share about whether the string name passed into create should match the handle? i.e. //1) object declared, with handle name m_xyz_agent xyz_agent m_xyz_agent; //2) object created. what-string-name will you pass in to ::create? m_xyz_agent or smthg else? m_xyz_agent = xyz_agent::type_id::create("what-string-name",this); When I first started with uvm, I was tripped up a bunch in situations where I confused the handle and the string. A prime example is in the place of what-string-name below. uvm_config_db#(uvm_object_wrapper)::set(this,"*.what-string-name.asdf.main_phase", "default_sequence",xyz_seq::type_id::get()); When different developers use different styles, it can be a headache. So, besides suggesting 'just be consistent', which I fully agree with, what are your preferences, and why? thanks, Most examples I find have the string name passed to create and the handle match. (Having them differ does help a newbie understand what is going on a bit better, I believe.) -
Hi, experts, I met one problem when i use type_id::create() to create one instance of a component object. Here are my codes: typedef class tmp_for_test; class config_agent extends uvm_agent; typedef config_agent this_type; tmp_for_test #(int, byte) tmp_f_t; // Provide implmentations of virtual methods such as get_type_name and create `uvm_component_utils_begin(config_agent) `uvm_field_object(tmp_f_t, UVM_DEFAULT); `uvm_component_utils_end // new function new (string name, uvm_component parent); super.new(name, parent); endfunction : new // build_phase function void build_phase(uvm_phase phase); super.build_phase(phase); ... tmp_f_t = tmp_for_test#(int, byte)::type_id::create("tmp_f_t", this); ... endfunction: build_phase ... endclass: config_agent class tmp_for_test #(type T1=int, type T2=T1) extends uvm_component; T1 width; T2 depth; // Provide implmentations of virtual methods such as get_type_name and create `uvm_component_utils(tmp_for_test) function new (string name, uvm_component parent); super.new(name, parent); ... endfunction function void build_phase(uvm_phase phase); super.build_phase(phase); endfunction: build_phase ... endclass : tmp_for_test The VCS reports such an error: Error-[sV-ICA] Illegal class assignment ../sv_for_tmptest/02_master/config/config_agent.sv, 254 "this.tmp_f_t = uvm_pkg_uvm_component_registry_541795153::create("tmp_f_t", this, "\000");" Expression 'uvm_pkg_uvm_component_registry_541795153::create("tmp_f_t", this, "\000")' on rhs is not a class or a compatible class and hence cannot be assigned to a class handle on lhs. Please make sure that the lhs and rhs expressions are compatible. But it's okay when i use config_driver which extends uvm_driver replacing the class tmp_for test. Does anybody meet the same problem or know the reason? Thanks in advance
