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Showing results for tags 'co-simulation'.
I made some examples of SystemC testbench embedding Python, gnuplot. This SystemC testbench can run under ModelSim. With SystemC, I'm sure, there's no need to use weird procedural language interface. If you're interest in this issue, visit and read ad-free my blog page about HLS. Sorrily, it's written in Korean, but there's google translation service. You can find down link to download design sources. https://hls-goodkook.blogspot.com/2021/09/3-c-c-validation.html
I have used Modelsim to compare simulation results between a C model encapsulated in SystemC to its VHDL implementation, mostly with a GUI, for hardware verification. I am trying to see how SystemC can be used for Software validation and/or regression testing using a SystemC testbench that has software modules, SystemC models, and VHDL HW modules when fidelity is needed. I am assuming the open-source SystemC simulator does not support VHDL natively so a VHDL simulator would be needed like modelsim. What is the best way to use the SystemC open source simulation to make calls to a VHDL simulator like modelsim while reducing the license usage of modelsim? Can you share your experience and lessons learned regarding mixed language sims? Thanks Paul