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Hi, I was having few questions regarding clock usage in tlm.These are as folllows:- 1.I wanted to know whether we can supply clock to initiator and target modules. 2.If it can be used ,then how to do we need need to connect to modules.Like instantiate clock in top module and how should we do port or named mapping ? If not,then why its not used ? Because i havent come across any examples in tlm which uses clocks. 3.If we are using blocking interface then using wait statement,just that data doesnot get overidden. And if its a case of nb_interface then we are using delay statements . My question here would be,can i create system clock input port and connect them ? I had tried but i had got a failed port mapping error message. Thanks & regards, Shubham

Hi, I have came across this counter example from other website. Can u please tell me ,where have we intitialised the main clock. I know the default time period is 1ps,but i am not getting the start of the clock is from which point. I am not knowing the reason for its generation in waveform viewer. Thank you. Below is the code: #include "systemc.h" #include "design.cpp" int sc_main (int argc, char* argv[]) { sc_signal<bool> clock; sc_signal<bool> reset; sc_signal<bool> enable; sc_signal<sc_uint<4> > counter_out; int i = 0; // Connect the DUT first_counter counter("COUNTER"); counter.clock(clock); counter.reset(reset); counter.enable(enable); counter.counter_out(counter_out); sc_start(1, SC_NS); // Open VCD file sc_trace_file *wf = sc_create_vcd_trace_file("counter"); // Dump the desired signals sc_trace(wf, clock, "clock"); sc_trace(wf, reset, "reset"); sc_trace(wf, enable, "enable"); sc_trace(wf, counter_out, "count"); // Initialize all variables reset = 0; // initial value of reset enable = 0; // initial value of enable for (i=0;i<5;i++) { clock = 0; sc_start(1, SC_NS); clock = 1; sc_start(1, SC_NS); } reset = 1; // Assert the reset cout << "@" << sc_time_stamp() <<" Asserting reset\n" << endl; for (i=0;i<10;i++) { clock = 0; sc_start(1, SC_NS); clock = 1; sc_start(1, SC_NS); } reset = 0; // De-assert the reset cout << "@" << sc_time_stamp() <<" De-Asserting reset\n" << endl; for (i=0;i<5;i++) { clock = 0; sc_start(1, SC_NS); clock = 1; sc_start(1, SC_NS); } cout << "@" << sc_time_stamp() <<" Asserting Enable\n" << endl; enable = 1; // Assert enable for (i=0;i<20;i++) { clock = 0; sc_start(1, SC_NS); clock = 1; sc_start(1, SC_NS); } cout << "@" << sc_time_stamp() <<" De-Asserting Enable\n" << endl; enable = 0; // De-assert enable cout << "@" << sc_time_stamp() <<" Terminating simulation\n" << endl; sc_close_vcd_trace_file(wf); return 0;// Terminate simulation }

Hi all, i'm implementing a timer/counter(8-bit) that should not increment on every clock and i'm not supposed to provide any input clock port . But i need clock period in my design so my question is " How would i provide clock period(through constructor)?" here is the link to my working code on EDAplayground : http://www.edaplayground.com/x/4_dY if there is any problem in my code please feel free to tell me. regards, jatin