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Hello everybody, While working on a systemC project, I discovered that probably I have some confused ideas about signals and ports. Let's say I have something like this: //cell.hpp SC_MODULE(Cell) { sc_in<sc_uint<16> > datain; sc_in<sc_uint<1> > addr_en; sc_in<sc_uint<1> > enable; sc_out<sc_uint<16> > dataout; SC_CTOR(Cell) { SC_THREAD(memory_cell); sensitive << enable << datain << addr_en; } private: void memory_cell(); }; //cell.cpp void Cell::memory_cell() { unsign
