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Showing results for tags 'beta2'.
Hi, I started to play around with the basic scoreboard example provided in the uvm-systemC 1.0 beta 2 release. I was trying to enhance the example by adding a clock and a reset signal in the sc_main. Then I wanted to modify the vip_if to add a reset and clock signal. My goal was to implement a driver/monitor run phase that drives/samples the sig_data signal on the rising edge of the clock. I am struggling to do so... Is there such an example that exists or that someone could share ?