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Found 5 results

  1. Hi, How to handle memories wide 8 bits in my register model when register map is built with 32 bits width? Thank you Kristina
  2. I am working an a block that requires two different type of buffer descriptors, let call them bd_base, bd_ext. bd_base is size 8 bytes and bd_ext is size 32 bytes. These are implemented on a 64 bit (8 byte) bus/memory. For now I set the memory size to be 'd100000 with datasize 64bits. I have ran a simulation with bd_base which vreg size is equal to the bus width and the increment to the next vreg[i+1] is correct. However, when running with bd_ext with vreg size=32 bytes (4x the size of the bus), the increment to the next vreg[i+1] is off. The offset for a particular example for eac
  3. Hi, I'm trying to perform backdoor access to uvm_mem. For some reason, the Xcheck_accessX function in uvm_mem, override my map with pseudo map. From this function: rw.map = uvm_reg_map::backdoor(); From uvm_reg_map: // Function: backdoor // Return the backdoor pseudo-map singleton // // This pseudo-map is used to specify or configure the backdoor // instead of a real address map. // I need an important data from my map (the uvm_mem base address). why to override it? How can I overcome this? Thanks, Dror
  4. I am working on a design that supports single, or bursting access to a memory. I would like to keep the abstraction of the register model (ie. MEM.Write(), MEM.bust_write()...). It appears that the register model breaks up the burst-ed writes into single transactions. What is the best way to implement a burst_write (Basically one address, and many data items) into a single seq_item for the driver to implement?
  5. Is it possible to increment address by 8 in burst_read/burst_write functions from uvm_mem?
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