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  1. Hi, All - Hoping for a little help on this one. I have a very simple UVM register testbench but am having troubles getting it to work and having troubles figuring out the correct way to start the tests (there is lots of documentation on UVM REG setup except the final step of starting the test). Below is the error messages, the env.sv fle and the test1.sv file that I am using. I would be happy to tar-up the entire example if someone would like to look at more of my files. Thanks to anyone who can figure out this problem. Regards - Cliff # UVM_INFO verilog_src/uvm-1.1d/src/reg/uvm_reg_map.svh(1062) @ 0: reporter [REG_NO_ADAPT] Adapter not specified for map 'model.dutmap'. Accesses via this map will send abstract 'uvm_reg_item' items to sequencer 'uvm_test_top.e.agnt.sqr' # UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(272) @ 0: reporter [Questa UVM] End Of Elaboration # UVM_INFO verilog_src/uvm-1.1d/src/seq/uvm_sequencer_base.svh(1385) @ 0: uvm_test_top.e.agnt.sqr [PHASESEQ] No default phase sequence for phase 'run' # UVM_INFO tb_driver.sv(40) @ 0: uvm_test_top.e.agnt.drv [iNIT] Initialize (time @0) # UVM_FATAL @ 0: reporter@@seq [sEQ] neither the item's sequencer nor dedicated sequencer has been supplied to start item in seq class env extends uvm_env; `uvm_component_utils(env) tb_agent agnt; dutblk model; // Register model object reg2dut_adapter reg2dut; // Bus adapter object uvm_reg_predictor#(trans1) predict; // predictor component function new (string name, uvm_component parent); super.new(name, parent); endfunction function void build_phase(uvm_phase phase); super.build_phase(phase); agnt = tb_agent::type_id::create("agnt", this); model = dutblk::type_id::create("model"); reg2dut = reg2dut_adapter::type_id::create("reg2dut"); predict = uvm_reg_predictor#(trans1)::type_id::create("predict", this); model.build(); model.lock_model(); uvm_config_db#(dutblk)::set(uvm_root::get(),"*","reg_model", model); endfunction function void connect_phase(uvm_phase phase); super.connect_phase(phase); model.dutmap.set_sequencer(agnt.sqr); predict.map = model.dutmap; predict.adapter = reg2dut; // connect the predictor to the bus agent monitor analysis port agnt.aport.connect(predict.bus_in); endfunction endclass class test1 extends uvm_test; `uvm_component_utils(test1) env e; function new (string name, uvm_component parent); super.new(name, parent); endfunction function void build_phase(uvm_phase phase); super.build_phase(phase); e = env::type_id::create("e", this); endfunction task run_phase(uvm_phase phase); tr_sequence seq; seq = tr_sequence::type_id::create("seq"); //---------------------------------------- phase.raise_objection(this); //`uvm_do(seq) seq.start(null); phase.drop_objection(this); endtask endclass
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