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Showing results for tags 'READ'.
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Use of wait statement
Nimesh posted a topic in UVM SystemVerilog DiscussionsI have to write a code that can be synthesised in verilog language and it displays a few values. I need to display the read and write data being read/written to some registers using the AHB protocol. I successfully displayed the write data but I am stuck in displaying the read data. Since the read appears after some time, I couldn't find a way to capture and display the read data. Initially I thought of this : @(negedge clk) wait(rdata) $fdisplay(rdata) But there could be multiple non-zero Read transactions. Now i am stuck here : @(negedge clk) //wait for rdata to change $fdisplay(rdata) I am new to verilog and SystemVerilog. Please help Thank you
Read from buffer without removing content
Effiong posted a topic in SystemC LanguageHi all, I want to be able to read an element from a "buffer-like" data structure without removing it. Is there a systemc structure for that ? sc_fifo "nb_read() and read()" methods removes the element from the buffer. I want to be able to decide when to remove or not remove the data. Thanks
Hi there From the UVM users guide, a register read access can be executed as reg_model.BLK1.REG_FILE1.REG_1.read(status, rdata); But this mandates us to know the hierarchy of the register instantiation. ie., 'reg_model.BLK1.REG_FILE1' needs to be known to execute a read on register 'REG_1'. Is it possible to perform read/write access based on address instead of this hierarchy? Something like: generic_uvm_read (.address(0x0), rdata); In otherwords, we need not even know the register type or register instantiation hierarchy to issue a read access to that register. Can this be performed with UVM_REG? Requesting thoughts here. Best regards Balasubramanian G