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Found 4 results

  1. I am using Cygwin to run my commands in a Windows system So from bash prompt I am runnning the command.So Vsim opens in GUI mode and starts executing my script. vsim -i -do "source my_script.tcl" I am running a vsim command like this vsim -novopt -assertdebug -sv_seed random -coverage -onfinish stop -c -do "echo $Sv_Seed; add wave -r /*; run -all; coverage save -onexit ./coverage_database/my_test$Sv_Seed.ucdb;" my_top -l ./sim_log/my_test$Sv_Seed.log +UVM_TESTNAME=my_test +UVM_VERBOSITY=UVM_LOW But I am getting a message in questasim Warning: Ignoring nested -do argument: This is not taking the do commands in the vsim line.is there any option to solve this issue??
  2. Hi, I am trying to run uvm code using qverilog command using shell script as : qverilog \ -timescale "1ns/1ns" \ -mfcu \ +acc=rmb \ +incdir+../../../../../src+../sv\ ../../../../../src/uvm.sv\ $TB_HOME/tb_top.sv \ -R \ -sv_lib ../../../../../win32/uvm_dpi -supress 2181\ +UVM_TESTNAME=$TEST_NAME\ -c \ -do "run -all; q" \ -l questa.log I get the error as : ** Error: ../../../../../src/uvm_pkg.sv(27): near "package": syntax error, unexpected IDENTIFIER, expecting class ./examples/tb_top.sv: line 1: ///*-----------------------------------------------------------------: No such file or directory ./examples/tb_top.sv: line 2: //File: No such file or directory Where starting lines of tb_top are commented, but it is expecting file names there. Please help. Regards, Chandan
  3. I am using QuestaSim 10.3a_1 and try to record a dynamic array in the sequence item. But it doesn't show in the waveform window. When I try to fix the array size and use uvm_field_sarray_int to record it, it works well and data show as expected in the waveform windows. My code: # sequence item parameter int P_BIT_DEPTH = 10; rand int unsigned data_len; rand bit unsigned [P_BIT_DEPTH-1:0] data []; ... `uvm_field_array_int(data, UVM_ALL_ON+UVM_UNSIGNED) `uvm_field_int (data_len, UVM_ALL_ON+UVM_UNSIGNED) ... constraint c_data_size { data.size() == data_len; }; constraint c_data_size_order { solve data_len before data; }; # Sequence body task start_item(req); if (! req.randomize() with { data_len == 2; }) `uvm_error(tID, "Can't randomize ingress packet") finish_item(req); req.sprintf() always prints the right information, no matter data is dynamic or static array.
  4. Can anyone here recommend me chapters needed to read in questasim user guide so as to simulate uvm systemverilog environment ,, let's have assumption that I have no knowledge about simulator commands interface ,,, thanks in advance
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