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Found 8 results

  1. I have a DUT which will require multiple BFMs to handle the pin-wiggling of different sets of pins of the DUT. What I am wondering is whether it is possible to write just one driver class (monitor may be a different story), but then instantiate it for each of the BFMs. I have explored the technique of Polymorphic Interfaces to allow Drivers to hold a handle to the base abstract class for which each BFM interface will instantiate a "concrete" class inheriting from the abstract class in order to be type compatible. The uvm_config_db could be used to help each Driver "get" their respective "confi
  2. Q1) I'd like confirmation that the following waits for a posedge of clk are identical. (The code it refers to is far below.) 1) @(posedge my_play_if.clock); or @(posedge clk); 2) @(my_play_if.cb1); Q2) I'd also like to confirm that input and output clocking_skew of a clocking block have no effect on the inputs of the interface. They only affect the inputs and outputs of that clocking block. I'm pretty confident about both of these and the SystemVerilog LRM seems clear, but I want to confirm while I am cleaning up some inherited code which is not currently working. Referenc
  3. Dear all, I'd like to access a register via multiple physical interfaces (bfm). Is it possible to set 2 different sequencers to the registers with same address? I have read this is a known issue from this forum. Could anybody give me a good example? I'm looking for a solution that there is no problem in prediction as well as write/read of UVM_REG. Thanks & Regards,
  4. Hello, The question is SystemVerilog specific, not related to UVM. I was wondering if it is possible to initialize an interface inside an internal module A and further pass it to an another module B, which is at the same level of hierarchy as the module A. interface Inter (input logic clk); logic a; endinterface module A(Inter inter); logic clk; Inter inter(clk); endmodule module B(Inter inter); always_ff @(posedge inter.clk) ..... endmodule module top; A a( .* ); B b( .* ); endmodule Let's assume module A is a master of some Stream interface (like AXI4-Stream),
  5. Hi, I have a question when I use uvm_config_db for interface connection. Generally, I know we use set() and get() function of "uvm_config_db" when we connect interface instance with virtual interface. As I know, uvm_config_db#(virtual aaa_intf)::set() is described inside top testbench module. And uvm_config_db#(virtual aaa_intf)::get() is some phase of inside class. What I want to do is to move set() function into some phase of class. Is it possible? If possible, which phase can I use not to be no problem in topology? Could you give me an example? I generally descirbes
  6. Hi In System Verilog the recommended approach to create interfaces is through modport suppose I have an interface like interface axi_if(input clk, input rst); logic arlen; clocking mclk@(posedge clk); output arlen; endclocking modport Master(clocking mclk, input clk, input rst); endinterface In Bind we can bind a module to an interface if all the ports are in the portlist. So is there someway I can bind arlen though it is not defined in the interface port list?
  7. May a module or interface have default 'no-connect' port connections, for ports that we don't need to connect? I need to use an interface which is shared between testbenches. I instantiate it a lot and don't use many of the ports (i.e. they can be 'no connects') Using Cadence irun, I get this warning when I don't connect inputs to the interface: ncelab: *W,CUVWSI With tasks/functions, I can have a default value for an input argument. Is there anything similar for interfaces (or modules for that matter)? Rather than creating a bunch of dummy inputs for these ports that are not
  8. Hi, I have a interface monitor where i am capturing data from the interface. I need to pass valid data captured from the interface to the scoreboard for comparison. But the behaviour of interface signals and the way they are asserted depends on the register configuration. Now this config info is not known to the interface or the interface monitor. So while implementing the monitor, should i define two monitors 1) interface monitor which just samples all the data from the bus. 2) process data got in 1) furthur depending on the register config & then pass it on the scoreboard fo
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