Search the Community
Showing results for tags 'HIGH LEVEL SYNTHESIS'.
Found 1 result
systemC TLM projects
KARTHIKEYAN posted a topic in SystemC TLM (Transaction-level Modeling)hai to all Iam karthik,doing my masters in VLSI DESIGN ,i found my interest in system level design and i wish to do project in systemcTLM based simulation.As a starter ,learning systemC language and i want to learn how systemc TLM differ by verilog,VHDL and other languages by results.i.e by simulation...kindly guide me regarding by suggesting some projects or papers in these domains.. keywords:co-simulation,systemc based simulations..