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Q1) How well do the major simulators support SystemVerilog checkers (1800-2012.pdf Section 17.)? Q2) In (the) UVM, do you think there is a place for checkers? Context) We have VHDL rtl. For the data-interface between modules ABC and XYZ, we want to consolidate our protocol checking. case1) ABC testbench. We now have the protocol checking in the sv interface which ABC and XYZ share case2) XYZ testbench. the same case3) Top level testbench (testing DUT which instantiates ABC and XYZ). Either we have to move the protocol checking to a module which is bind-ed to the VH